1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK 2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK 3 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK 4 5 ; EG-CHECK: @u32_mul24 6 ; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W 7 ; SI-CHECK: @u32_mul24 8 ; SI-CHECK: V_MUL_U32_U24 9 10 define void @u32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) { 11 entry: 12 %0 = shl i32 %a, 8 13 %a_24 = lshr i32 %0, 8 14 %1 = shl i32 %b, 8 15 %b_24 = lshr i32 %1, 8 16 %2 = mul i32 %a_24, %b_24 17 store i32 %2, i32 addrspace(1)* %out 18 ret void 19 } 20 21 ; EG-CHECK: @i16_mul24 22 ; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40 23 ; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44 24 ; The order of A and B does not matter. 25 ; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]] 26 ; The result must be sign-extended 27 ; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x 28 ; EG-CHECK: 16 29 ; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x 30 ; EG-CHECK: 16 31 ; SI-CHECK: @i16_mul24 32 ; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}} 33 ; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 16, [[MUL]] 34 ; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 16, [[LSHL]] 35 36 define void @i16_mul24(i32 addrspace(1)* %out, i16 %a, i16 %b) { 37 entry: 38 %0 = mul i16 %a, %b 39 %1 = sext i16 %0 to i32 40 store i32 %1, i32 addrspace(1)* %out 41 ret void 42 } 43 44 ; EG-CHECK: @i8_mul24 45 ; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40 46 ; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44 47 ; The order of A and B does not matter. 48 ; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]] 49 ; The result must be sign-extended 50 ; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x 51 ; EG-CHECK: 24 52 ; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x 53 ; EG-CHECK: 24 54 ; SI-CHECK: @i8_mul24 55 ; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}} 56 ; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 24, [[MUL]] 57 ; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 24, [[LSHL]] 58 59 define void @i8_mul24(i32 addrspace(1)* %out, i8 %a, i8 %b) { 60 entry: 61 %0 = mul i8 %a, %b 62 %1 = sext i8 %0 to i32 63 store i32 %1, i32 addrspace(1)* %out 64 ret void 65 } 66
