1 ; Function Attrs: nounwind 2 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s 3 ; 4 ; CFG flattening should use parallel-and mode to generate branch conditions and 5 ; then merge if-regions with the same bodies. 6 ; 7 ; CHECK: AND_INT 8 ; CHECK-NEXT: AND_INT 9 ; CHECK-NEXT: OR_INT 10 define void @_Z9chk1D_512v() #0 { 11 entry: 12 %a0 = alloca i32, align 4 13 %b0 = alloca i32, align 4 14 %c0 = alloca i32, align 4 15 %d0 = alloca i32, align 4 16 %a1 = alloca i32, align 4 17 %b1 = alloca i32, align 4 18 %c1 = alloca i32, align 4 19 %d1 = alloca i32, align 4 20 %data = alloca i32, align 4 21 %0 = load i32* %a0, align 4 22 %1 = load i32* %b0, align 4 23 %cmp = icmp ne i32 %0, %1 24 br i1 %cmp, label %land.lhs.true, label %if.end 25 26 land.lhs.true: ; preds = %entry 27 %2 = load i32* %c0, align 4 28 %3 = load i32* %d0, align 4 29 %cmp1 = icmp ne i32 %2, %3 30 br i1 %cmp1, label %if.then, label %if.end 31 32 if.then: ; preds = %land.lhs.true 33 store i32 1, i32* %data, align 4 34 br label %if.end 35 36 if.end: ; preds = %if.then, %land.lhs.true, %entry 37 %4 = load i32* %a1, align 4 38 %5 = load i32* %b1, align 4 39 %cmp2 = icmp ne i32 %4, %5 40 br i1 %cmp2, label %land.lhs.true3, label %if.end6 41 42 land.lhs.true3: ; preds = %if.end 43 %6 = load i32* %c1, align 4 44 %7 = load i32* %d1, align 4 45 %cmp4 = icmp ne i32 %6, %7 46 br i1 %cmp4, label %if.then5, label %if.end6 47 48 if.then5: ; preds = %land.lhs.true3 49 store i32 1, i32* %data, align 4 50 br label %if.end6 51 52 if.end6: ; preds = %if.then5, %land.lhs.true3, %if.end 53 ret void 54 } 55
