1 ; Test zero extensions from a halfword to an i32. 2 ; 3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5 ; Test register extension, starting with an i32. 6 define i32 @f1(i32 %a) { 7 ; CHECK-LABEL: f1: 8 ; CHECK: llhr %r2, %r2 9 ; CHECK: br %r14 10 %half = trunc i32 %a to i16 11 %ext = zext i16 %half to i32 12 ret i32 %ext 13 } 14 15 ; ...and again with an i64. 16 define i32 @f2(i64 %a) { 17 ; CHECK-LABEL: f2: 18 ; CHECK: llhr %r2, %r2 19 ; CHECK: br %r14 20 %half = trunc i64 %a to i16 21 %ext = zext i16 %half to i32 22 ret i32 %ext 23 } 24 25 ; Check ANDs that are equivalent to zero extension. 26 define i32 @f3(i32 %a) { 27 ; CHECK-LABEL: f3: 28 ; CHECK: llhr %r2, %r2 29 ; CHECK: br %r14 30 %ext = and i32 %a, 65535 31 ret i32 %ext 32 } 33 34 ; Check LLH with no displacement. 35 define i32 @f4(i16 *%src) { 36 ; CHECK-LABEL: f4: 37 ; CHECK: llh %r2, 0(%r2) 38 ; CHECK: br %r14 39 %half = load i16 *%src 40 %ext = zext i16 %half to i32 41 ret i32 %ext 42 } 43 44 ; Check the high end of the LLH range. 45 define i32 @f5(i16 *%src) { 46 ; CHECK-LABEL: f5: 47 ; CHECK: llh %r2, 524286(%r2) 48 ; CHECK: br %r14 49 %ptr = getelementptr i16 *%src, i64 262143 50 %half = load i16 *%ptr 51 %ext = zext i16 %half to i32 52 ret i32 %ext 53 } 54 55 ; Check the next halfword up, which needs separate address logic. 56 ; Other sequences besides this one would be OK. 57 define i32 @f6(i16 *%src) { 58 ; CHECK-LABEL: f6: 59 ; CHECK: agfi %r2, 524288 60 ; CHECK: llh %r2, 0(%r2) 61 ; CHECK: br %r14 62 %ptr = getelementptr i16 *%src, i64 262144 63 %half = load i16 *%ptr 64 %ext = zext i16 %half to i32 65 ret i32 %ext 66 } 67 68 ; Check the high end of the negative LLH range. 69 define i32 @f7(i16 *%src) { 70 ; CHECK-LABEL: f7: 71 ; CHECK: llh %r2, -2(%r2) 72 ; CHECK: br %r14 73 %ptr = getelementptr i16 *%src, i64 -1 74 %half = load i16 *%ptr 75 %ext = zext i16 %half to i32 76 ret i32 %ext 77 } 78 79 ; Check the low end of the LLH range. 80 define i32 @f8(i16 *%src) { 81 ; CHECK-LABEL: f8: 82 ; CHECK: llh %r2, -524288(%r2) 83 ; CHECK: br %r14 84 %ptr = getelementptr i16 *%src, i64 -262144 85 %half = load i16 *%ptr 86 %ext = zext i16 %half to i32 87 ret i32 %ext 88 } 89 90 ; Check the next halfword down, which needs separate address logic. 91 ; Other sequences besides this one would be OK. 92 define i32 @f9(i16 *%src) { 93 ; CHECK-LABEL: f9: 94 ; CHECK: agfi %r2, -524290 95 ; CHECK: llh %r2, 0(%r2) 96 ; CHECK: br %r14 97 %ptr = getelementptr i16 *%src, i64 -262145 98 %half = load i16 *%ptr 99 %ext = zext i16 %half to i32 100 ret i32 %ext 101 } 102 103 ; Check that LLH allows an index 104 define i32 @f10(i64 %src, i64 %index) { 105 ; CHECK-LABEL: f10: 106 ; CHECK: llh %r2, 524287(%r3,%r2) 107 ; CHECK: br %r14 108 %add1 = add i64 %src, %index 109 %add2 = add i64 %add1, 524287 110 %ptr = inttoptr i64 %add2 to i16 * 111 %half = load i16 *%ptr 112 %ext = zext i16 %half to i32 113 ret i32 %ext 114 } 115 116 ; Test a case where we spill the source of at least one LLHR. We want 117 ; to use LLH if possible. 118 define void @f11(i32 *%ptr) { 119 ; CHECK-LABEL: f11: 120 ; CHECK: llh {{%r[0-9]+}}, 16{{[26]}}(%r15) 121 ; CHECK: br %r14 122 %val0 = load volatile i32 *%ptr 123 %val1 = load volatile i32 *%ptr 124 %val2 = load volatile i32 *%ptr 125 %val3 = load volatile i32 *%ptr 126 %val4 = load volatile i32 *%ptr 127 %val5 = load volatile i32 *%ptr 128 %val6 = load volatile i32 *%ptr 129 %val7 = load volatile i32 *%ptr 130 %val8 = load volatile i32 *%ptr 131 %val9 = load volatile i32 *%ptr 132 %val10 = load volatile i32 *%ptr 133 %val11 = load volatile i32 *%ptr 134 %val12 = load volatile i32 *%ptr 135 %val13 = load volatile i32 *%ptr 136 %val14 = load volatile i32 *%ptr 137 %val15 = load volatile i32 *%ptr 138 139 %trunc0 = trunc i32 %val0 to i16 140 %trunc1 = trunc i32 %val1 to i16 141 %trunc2 = trunc i32 %val2 to i16 142 %trunc3 = trunc i32 %val3 to i16 143 %trunc4 = trunc i32 %val4 to i16 144 %trunc5 = trunc i32 %val5 to i16 145 %trunc6 = trunc i32 %val6 to i16 146 %trunc7 = trunc i32 %val7 to i16 147 %trunc8 = trunc i32 %val8 to i16 148 %trunc9 = trunc i32 %val9 to i16 149 %trunc10 = trunc i32 %val10 to i16 150 %trunc11 = trunc i32 %val11 to i16 151 %trunc12 = trunc i32 %val12 to i16 152 %trunc13 = trunc i32 %val13 to i16 153 %trunc14 = trunc i32 %val14 to i16 154 %trunc15 = trunc i32 %val15 to i16 155 156 %ext0 = zext i16 %trunc0 to i32 157 %ext1 = zext i16 %trunc1 to i32 158 %ext2 = zext i16 %trunc2 to i32 159 %ext3 = zext i16 %trunc3 to i32 160 %ext4 = zext i16 %trunc4 to i32 161 %ext5 = zext i16 %trunc5 to i32 162 %ext6 = zext i16 %trunc6 to i32 163 %ext7 = zext i16 %trunc7 to i32 164 %ext8 = zext i16 %trunc8 to i32 165 %ext9 = zext i16 %trunc9 to i32 166 %ext10 = zext i16 %trunc10 to i32 167 %ext11 = zext i16 %trunc11 to i32 168 %ext12 = zext i16 %trunc12 to i32 169 %ext13 = zext i16 %trunc13 to i32 170 %ext14 = zext i16 %trunc14 to i32 171 %ext15 = zext i16 %trunc15 to i32 172 173 store volatile i32 %val0, i32 *%ptr 174 store volatile i32 %val1, i32 *%ptr 175 store volatile i32 %val2, i32 *%ptr 176 store volatile i32 %val3, i32 *%ptr 177 store volatile i32 %val4, i32 *%ptr 178 store volatile i32 %val5, i32 *%ptr 179 store volatile i32 %val6, i32 *%ptr 180 store volatile i32 %val7, i32 *%ptr 181 store volatile i32 %val8, i32 *%ptr 182 store volatile i32 %val9, i32 *%ptr 183 store volatile i32 %val10, i32 *%ptr 184 store volatile i32 %val11, i32 *%ptr 185 store volatile i32 %val12, i32 *%ptr 186 store volatile i32 %val13, i32 *%ptr 187 store volatile i32 %val14, i32 *%ptr 188 store volatile i32 %val15, i32 *%ptr 189 190 store volatile i32 %ext0, i32 *%ptr 191 store volatile i32 %ext1, i32 *%ptr 192 store volatile i32 %ext2, i32 *%ptr 193 store volatile i32 %ext3, i32 *%ptr 194 store volatile i32 %ext4, i32 *%ptr 195 store volatile i32 %ext5, i32 *%ptr 196 store volatile i32 %ext6, i32 *%ptr 197 store volatile i32 %ext7, i32 *%ptr 198 store volatile i32 %ext8, i32 *%ptr 199 store volatile i32 %ext9, i32 *%ptr 200 store volatile i32 %ext10, i32 *%ptr 201 store volatile i32 %ext11, i32 *%ptr 202 store volatile i32 %ext12, i32 *%ptr 203 store volatile i32 %ext13, i32 *%ptr 204 store volatile i32 %ext14, i32 *%ptr 205 store volatile i32 %ext15, i32 *%ptr 206 207 ret void 208 } 209
