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      1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
      2 
      3 ; CHECK: vpaddq %ymm
      4 define <4 x i64> @test_vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
      5   %x = add <4 x i64> %i, %j
      6   ret <4 x i64> %x
      7 }
      8 
      9 ; CHECK: vpaddd %ymm
     10 define <8 x i32> @test_vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
     11   %x = add <8 x i32> %i, %j
     12   ret <8 x i32> %x
     13 }
     14 
     15 ; CHECK: vpaddw %ymm
     16 define <16 x i16> @test_vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
     17   %x = add <16 x i16> %i, %j
     18   ret <16 x i16> %x
     19 }
     20 
     21 ; CHECK: vpaddb %ymm
     22 define <32 x i8> @test_vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
     23   %x = add <32 x i8> %i, %j
     24   ret <32 x i8> %x
     25 }
     26 
     27 ; CHECK: vpsubq %ymm
     28 define <4 x i64> @test_vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
     29   %x = sub <4 x i64> %i, %j
     30   ret <4 x i64> %x
     31 }
     32 
     33 ; CHECK: vpsubd %ymm
     34 define <8 x i32> @test_vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
     35   %x = sub <8 x i32> %i, %j
     36   ret <8 x i32> %x
     37 }
     38 
     39 ; CHECK: vpsubw %ymm
     40 define <16 x i16> @test_vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
     41   %x = sub <16 x i16> %i, %j
     42   ret <16 x i16> %x
     43 }
     44 
     45 ; CHECK: vpsubb %ymm
     46 define <32 x i8> @test_vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
     47   %x = sub <32 x i8> %i, %j
     48   ret <32 x i8> %x
     49 }
     50 
     51 ; CHECK: vpmulld %ymm
     52 define <8 x i32> @test_vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
     53   %x = mul <8 x i32> %i, %j
     54   ret <8 x i32> %x
     55 }
     56 
     57 ; CHECK: vpmullw %ymm
     58 define <16 x i16> @test_vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
     59   %x = mul <16 x i16> %i, %j
     60   ret <16 x i16> %x
     61 }
     62 
     63 ; CHECK: mul-v4i64
     64 ; CHECK: vpmuludq %ymm
     65 ; CHECK-NEXT: vpsrlq $32, %ymm
     66 ; CHECK-NEXT: vpmuludq %ymm
     67 ; CHECK-NEXT: vpsllq $32, %ymm
     68 ; CHECK-NEXT: vpaddq %ymm
     69 ; CHECK-NEXT: vpsrlq $32, %ymm
     70 ; CHECK-NEXT: vpmuludq %ymm
     71 ; CHECK-NEXT: vpsllq $32, %ymm
     72 ; CHECK-NEXT: vpaddq %ymm
     73 define <4 x i64> @mul-v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
     74   %x = mul <4 x i64> %i, %j
     75   ret <4 x i64> %x
     76 }
     77 
     78 ; CHECK: mul_const1
     79 ; CHECK: vpaddd
     80 ; CHECK: ret
     81 define <8 x i32> @mul_const1(<8 x i32> %x) {
     82   %y = mul <8 x i32> %x, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
     83   ret <8 x i32> %y
     84 }
     85 
     86 ; CHECK: mul_const2
     87 ; CHECK: vpsllq  $2
     88 ; CHECK: ret
     89 define <4 x i64> @mul_const2(<4 x i64> %x) {
     90   %y = mul <4 x i64> %x, <i64 4, i64 4, i64 4, i64 4>
     91   ret <4 x i64> %y
     92 }
     93 
     94 ; CHECK: mul_const3
     95 ; CHECK: vpsllw  $3
     96 ; CHECK: ret
     97 define <16 x i16> @mul_const3(<16 x i16> %x) {
     98   %y = mul <16 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
     99   ret <16 x i16> %y
    100 }
    101 
    102 ; CHECK: mul_const4
    103 ; CHECK: vpxor
    104 ; CHECK: vpsubq
    105 ; CHECK: ret
    106 define <4 x i64> @mul_const4(<4 x i64> %x) {
    107   %y = mul <4 x i64> %x, <i64 -1, i64 -1, i64 -1, i64 -1>
    108   ret <4 x i64> %y
    109 }
    110 
    111 ; CHECK: mul_const5
    112 ; CHECK: vxorps
    113 ; CHECK-NEXT: ret
    114 define <8 x i32> @mul_const5(<8 x i32> %x) {
    115   %y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
    116   ret <8 x i32> %y
    117 }
    118 
    119 ; CHECK: mul_const6
    120 ; CHECK: vpmulld
    121 ; CHECK: ret
    122 define <8 x i32> @mul_const6(<8 x i32> %x) {
    123   %y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 2, i32 0, i32 2, i32 0, i32 0>
    124   ret <8 x i32> %y
    125 }
    126 
    127 ; CHECK: mul_const7
    128 ; CHECK: vpaddq
    129 ; CHECK: vpaddq
    130 ; CHECK: ret
    131 define <8 x i64> @mul_const7(<8 x i64> %x) {
    132   %y = mul <8 x i64> %x, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
    133   ret <8 x i64> %y
    134 }
    135 
    136 ; CHECK: mul_const8
    137 ; CHECK: vpsllw  $3
    138 ; CHECK: ret
    139 define <8 x i16> @mul_const8(<8 x i16> %x) {
    140   %y = mul <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
    141   ret <8 x i16> %y
    142 }
    143 
    144 ; CHECK: mul_const9
    145 ; CHECK: vpmulld
    146 ; CHECK: ret
    147 define <8 x i32> @mul_const9(<8 x i32> %x) {
    148   %y = mul <8 x i32> %x, <i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
    149   ret <8 x i32> %y
    150 }
    151