1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s 2 3 ; AVX2 Logical Shift Left 4 5 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) { 6 entry: 7 %shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 8 ret <16 x i16> %shl 9 } 10 11 ; CHECK-LABEL: test_sllw_1: 12 ; CHECK: vpsllw $0, %ymm0, %ymm0 13 ; CHECK: ret 14 15 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) { 16 entry: 17 %shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 18 ret <16 x i16> %shl 19 } 20 21 ; CHECK-LABEL: test_sllw_2: 22 ; CHECK: vpaddw %ymm0, %ymm0, %ymm0 23 ; CHECK: ret 24 25 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) { 26 entry: 27 %shl = shl <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> 28 ret <16 x i16> %shl 29 } 30 31 ; CHECK-LABEL: test_sllw_3: 32 ; CHECK: vxorps %ymm0, %ymm0, %ymm0 33 ; CHECK: ret 34 35 define <8 x i32> @test_slld_1(<8 x i32> %InVec) { 36 entry: 37 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 38 ret <8 x i32> %shl 39 } 40 41 ; CHECK-LABEL: test_slld_1: 42 ; CHECK: vpslld $0, %ymm0, %ymm0 43 ; CHECK: ret 44 45 define <8 x i32> @test_slld_2(<8 x i32> %InVec) { 46 entry: 47 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 48 ret <8 x i32> %shl 49 } 50 51 ; CHECK-LABEL: test_slld_2: 52 ; CHECK: vpaddd %ymm0, %ymm0, %ymm0 53 ; CHECK: ret 54 55 define <8 x i32> @test_slld_3(<8 x i32> %InVec) { 56 entry: 57 %shl = shl <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32> 58 ret <8 x i32> %shl 59 } 60 61 ; CHECK-LABEL: test_slld_3: 62 ; CHECK: vxorps %ymm0, %ymm0, %ymm0 63 ; CHECK: ret 64 65 define <4 x i64> @test_sllq_1(<4 x i64> %InVec) { 66 entry: 67 %shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0> 68 ret <4 x i64> %shl 69 } 70 71 ; CHECK-LABEL: test_sllq_1: 72 ; CHECK: vpsllq $0, %ymm0, %ymm0 73 ; CHECK: ret 74 75 define <4 x i64> @test_sllq_2(<4 x i64> %InVec) { 76 entry: 77 %shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1> 78 ret <4 x i64> %shl 79 } 80 81 ; CHECK-LABEL: test_sllq_2: 82 ; CHECK: vpaddq %ymm0, %ymm0, %ymm0 83 ; CHECK: ret 84 85 define <4 x i64> @test_sllq_3(<4 x i64> %InVec) { 86 entry: 87 %shl = shl <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64> 88 ret <4 x i64> %shl 89 } 90 91 ; CHECK-LABEL: test_sllq_3: 92 ; CHECK: vxorps %ymm0, %ymm0, %ymm0 93 ; CHECK: ret 94 95 ; AVX2 Arithmetic Shift 96 97 define <16 x i16> @test_sraw_1(<16 x i16> %InVec) { 98 entry: 99 %shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 100 ret <16 x i16> %shl 101 } 102 103 ; CHECK-LABEL: test_sraw_1: 104 ; CHECK: vpsraw $0, %ymm0, %ymm0 105 ; CHECK: ret 106 107 define <16 x i16> @test_sraw_2(<16 x i16> %InVec) { 108 entry: 109 %shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 110 ret <16 x i16> %shl 111 } 112 113 ; CHECK-LABEL: test_sraw_2: 114 ; CHECK: vpsraw $1, %ymm0, %ymm0 115 ; CHECK: ret 116 117 define <16 x i16> @test_sraw_3(<16 x i16> %InVec) { 118 entry: 119 %shl = ashr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> 120 ret <16 x i16> %shl 121 } 122 123 ; CHECK-LABEL: test_sraw_3: 124 ; CHECK: vpsraw $16, %ymm0, %ymm0 125 ; CHECK: ret 126 127 define <8 x i32> @test_srad_1(<8 x i32> %InVec) { 128 entry: 129 %shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 130 ret <8 x i32> %shl 131 } 132 133 ; CHECK-LABEL: test_srad_1: 134 ; CHECK: vpsrad $0, %ymm0, %ymm0 135 ; CHECK: ret 136 137 define <8 x i32> @test_srad_2(<8 x i32> %InVec) { 138 entry: 139 %shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 140 ret <8 x i32> %shl 141 } 142 143 ; CHECK-LABEL: test_srad_2: 144 ; CHECK: vpsrad $1, %ymm0, %ymm0 145 ; CHECK: ret 146 147 define <8 x i32> @test_srad_3(<8 x i32> %InVec) { 148 entry: 149 %shl = ashr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32> 150 ret <8 x i32> %shl 151 } 152 153 ; CHECK-LABEL: test_srad_3: 154 ; CHECK: vpsrad $32, %ymm0, %ymm0 155 ; CHECK: ret 156 157 ; SSE Logical Shift Right 158 159 define <16 x i16> @test_srlw_1(<16 x i16> %InVec) { 160 entry: 161 %shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 162 ret <16 x i16> %shl 163 } 164 165 ; CHECK-LABEL: test_srlw_1: 166 ; CHECK: vpsrlw $0, %ymm0, %ymm0 167 ; CHECK: ret 168 169 define <16 x i16> @test_srlw_2(<16 x i16> %InVec) { 170 entry: 171 %shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 172 ret <16 x i16> %shl 173 } 174 175 ; CHECK-LABEL: test_srlw_2: 176 ; CHECK: vpsrlw $1, %ymm0, %ymm0 177 ; CHECK: ret 178 179 define <16 x i16> @test_srlw_3(<16 x i16> %InVec) { 180 entry: 181 %shl = lshr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> 182 ret <16 x i16> %shl 183 } 184 185 ; CHECK-LABEL: test_srlw_3: 186 ; CHECK: vxorps %ymm0, %ymm0, %ymm0 187 ; CHECK: ret 188 189 define <8 x i32> @test_srld_1(<8 x i32> %InVec) { 190 entry: 191 %shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 192 ret <8 x i32> %shl 193 } 194 195 ; CHECK-LABEL: test_srld_1: 196 ; CHECK: vpsrld $0, %ymm0, %ymm0 197 ; CHECK: ret 198 199 define <8 x i32> @test_srld_2(<8 x i32> %InVec) { 200 entry: 201 %shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 202 ret <8 x i32> %shl 203 } 204 205 ; CHECK-LABEL: test_srld_2: 206 ; CHECK: vpsrld $1, %ymm0, %ymm0 207 ; CHECK: ret 208 209 define <8 x i32> @test_srld_3(<8 x i32> %InVec) { 210 entry: 211 %shl = lshr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32> 212 ret <8 x i32> %shl 213 } 214 215 ; CHECK-LABEL: test_srld_3: 216 ; CHECK: vxorps %ymm0, %ymm0, %ymm0 217 ; CHECK: ret 218 219 define <4 x i64> @test_srlq_1(<4 x i64> %InVec) { 220 entry: 221 %shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0> 222 ret <4 x i64> %shl 223 } 224 225 ; CHECK-LABEL: test_srlq_1: 226 ; CHECK: vpsrlq $0, %ymm0, %ymm0 227 ; CHECK: ret 228 229 define <4 x i64> @test_srlq_2(<4 x i64> %InVec) { 230 entry: 231 %shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1> 232 ret <4 x i64> %shl 233 } 234 235 ; CHECK-LABEL: test_srlq_2: 236 ; CHECK: vpsrlq $1, %ymm0, %ymm0 237 ; CHECK: ret 238 239 define <4 x i64> @test_srlq_3(<4 x i64> %InVec) { 240 entry: 241 %shl = lshr <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64> 242 ret <4 x i64> %shl 243 } 244 245 ; CHECK-LABEL: test_srlq_3: 246 ; CHECK: vxorps %ymm0, %ymm0, %ymm0 247 ; CHECK: ret 248
