1 ;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \ 2 ;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \ 3 ;; RUN: -filetype=obj %s -o - | \ 4 ;; RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s 5 6 ;; FIXME: This file needs to be in .s form! 7 ;; The args to llc are there to constrain the codegen only. 8 ;; 9 ;; Ensure no regression on ARM/gcc compatibility for 10 ;; emitting explicit symbol relocs for nonexternal symbols 11 ;; versus section symbol relocs (with offset) - 12 ;; 13 ;; Default llvm behavior is to emit as section symbol relocs nearly 14 ;; everything that is not an undefined external. Unfortunately, this 15 ;; diverges from what codesourcery ARM/gcc does! 16 ;; 17 ;; Tests that reloc to .L.str* show up as explicit symbols 18 19 target triple = "armv7-none-linux-gnueabi" 20 21 @.str = private constant [7 x i8] c"@null\0A\00", align 4 22 @.str1 = private constant [8 x i8] c"@write\0A\00", align 4 23 @.str2 = private constant [13 x i8] c"hello worldn\00", align 4 24 @.str3 = private constant [7 x i8] c"@exit\0A\00", align 4 25 26 declare i32 @mystrlen(i8* nocapture %s) nounwind readonly 27 28 declare void @myhextochar(i32 %n, i8* nocapture %buffer) nounwind 29 30 define i32 @main() nounwind { 31 entry: 32 %0 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind 33 %1 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind 34 %2 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind 35 %3 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind 36 tail call void @exit(i32 55) noreturn nounwind 37 unreachable 38 } 39 40 declare i32 @write(...) 41 42 declare void @exit(i32) noreturn nounwind 43 44 ;; OBJ: Relocations [ 45 ;; OBJ: Section (2) .rel.text { 46 ;; OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str 47 ;; OBJ: } 48 ;; OBJ: ] 49
