1 /************************************************************************** 2 3 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and 4 Tungsten Graphics Inc, Cedar Park, TX. 5 6 All Rights Reserved. 7 8 Permission is hereby granted, free of charge, to any person obtaining a 9 copy of this software and associated documentation files (the "Software"), 10 to deal in the Software without restriction, including without limitation 11 on the rights to use, copy, modify, merge, publish, distribute, sub 12 license, and/or sell copies of the Software, and to permit persons to whom 13 the Software is furnished to do so, subject to the following conditions: 14 15 The above copyright notice and this permission notice (including the next 16 paragraph) shall be included in all copies or substantial portions of the 17 Software. 18 19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 22 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 23 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 24 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 25 USE OR OTHER DEALINGS IN THE SOFTWARE. 26 27 **************************************************************************/ 28 29 /* 30 * Authors: 31 * Keith Whitwell <keith (at) tungstengraphics.com> 32 * 33 */ 34 35 #include <errno.h> 36 37 #include "main/glheader.h" 38 #include "main/imports.h" 39 40 #include "r200_context.h" 41 #include "r200_sanity.h" 42 #include "radeon_reg.h" 43 #include "r200_reg.h" 44 45 /* Set this '1' to get more verbiage. 46 */ 47 #define MORE_VERBOSE 1 48 49 #if MORE_VERBOSE 50 #define VERBOSE (R200_DEBUG & RADEON_VERBOSE) 51 #define NORMAL (1) 52 #else 53 #define VERBOSE 0 54 #define NORMAL (R200_DEBUG & RADEON_VERBOSE) 55 #endif 56 57 58 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 59 * 1.3 cmdbuffers allow all previous state to be updated as well as 60 * the tcl scalar and vector areas. 61 */ 62 static struct { 63 int start; 64 int len; 65 const char *name; 66 } packet[RADEON_MAX_STATE_PACKETS] = { 67 { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, 68 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, 69 { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, 70 { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, 71 { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, 72 { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, 73 { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, 74 { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, 75 { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, 76 { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, 77 { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, 78 { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, 79 { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, 80 { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, 81 { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, 82 { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, 83 { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, 84 { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, 85 { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, 86 { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, 87 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, 88 { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" }, 89 { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, 90 { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, 91 { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, 92 { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, 93 { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, 94 { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, 95 { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, 96 { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, 97 { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, 98 { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, 99 { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, 100 { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, 101 { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, 102 { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, 103 { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, 104 { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, 105 { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, 106 { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, 107 { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, 108 { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, 109 { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, 110 { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, 111 { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, 112 { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, 113 { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, 114 { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, 115 { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, 116 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, 117 { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, 118 { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, 119 { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, 120 { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, 121 { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, 122 { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, 123 { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, 124 { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, 125 { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, 126 { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, 127 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, 128 { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ 129 { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ 130 { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, 131 { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, 132 { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, 133 { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, 134 { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, 135 { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, 136 { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, 137 { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, 138 { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, 139 { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, 140 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, 141 { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, 142 { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, 143 { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, 144 { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, 145 { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" }, 146 { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" }, 147 { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" }, 148 { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" }, 149 { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" }, 150 { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" }, 151 { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" }, 152 { R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ 153 { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, 154 { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 155 { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 156 { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 157 { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 158 { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 159 { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 160 { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 161 { R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, 162 }; 163 164 struct reg_names { 165 int idx; 166 const char *name; 167 }; 168 169 static struct reg_names reg_names[] = { 170 { R200_PP_MISC, "R200_PP_MISC" }, 171 { R200_PP_FOG_COLOR, "R200_PP_FOG_COLOR" }, 172 { R200_RE_SOLID_COLOR, "R200_RE_SOLID_COLOR" }, 173 { R200_RB3D_BLENDCNTL, "R200_RB3D_BLENDCNTL" }, 174 { R200_RB3D_DEPTHOFFSET, "R200_RB3D_DEPTHOFFSET" }, 175 { R200_RB3D_DEPTHPITCH, "R200_RB3D_DEPTHPITCH" }, 176 { R200_RB3D_ZSTENCILCNTL, "R200_RB3D_ZSTENCILCNTL" }, 177 { R200_PP_CNTL, "R200_PP_CNTL" }, 178 { R200_RB3D_CNTL, "R200_RB3D_CNTL" }, 179 { R200_RB3D_COLOROFFSET, "R200_RB3D_COLOROFFSET" }, 180 { R200_RE_WIDTH_HEIGHT, "R200_RE_WIDTH_HEIGHT" }, 181 { R200_RB3D_COLORPITCH, "R200_RB3D_COLORPITCH" }, 182 { R200_SE_CNTL, "R200_SE_CNTL" }, 183 { R200_RE_CNTL, "R200_RE_CNTL" }, 184 { R200_RE_MISC, "R200_RE_MISC" }, 185 { R200_RE_STIPPLE_ADDR, "R200_RE_STIPPLE_ADDR" }, 186 { R200_RE_STIPPLE_DATA, "R200_RE_STIPPLE_DATA" }, 187 { R200_RE_LINE_PATTERN, "R200_RE_LINE_PATTERN" }, 188 { R200_RE_LINE_STATE, "R200_RE_LINE_STATE" }, 189 { R200_RE_SCISSOR_TL_0, "R200_RE_SCISSOR_TL_0" }, 190 { R200_RE_SCISSOR_BR_0, "R200_RE_SCISSOR_BR_0" }, 191 { R200_RE_SCISSOR_TL_1, "R200_RE_SCISSOR_TL_1" }, 192 { R200_RE_SCISSOR_BR_1, "R200_RE_SCISSOR_BR_1" }, 193 { R200_RE_SCISSOR_TL_2, "R200_RE_SCISSOR_TL_2" }, 194 { R200_RE_SCISSOR_BR_2, "R200_RE_SCISSOR_BR_2" }, 195 { R200_RB3D_DEPTHXY_OFFSET, "R200_RB3D_DEPTHXY_OFFSET" }, 196 { R200_RB3D_STENCILREFMASK, "R200_RB3D_STENCILREFMASK" }, 197 { R200_RB3D_ROPCNTL, "R200_RB3D_ROPCNTL" }, 198 { R200_RB3D_PLANEMASK, "R200_RB3D_PLANEMASK" }, 199 { R200_SE_VPORT_XSCALE, "R200_SE_VPORT_XSCALE" }, 200 { R200_SE_VPORT_XOFFSET, "R200_SE_VPORT_XOFFSET" }, 201 { R200_SE_VPORT_YSCALE, "R200_SE_VPORT_YSCALE" }, 202 { R200_SE_VPORT_YOFFSET, "R200_SE_VPORT_YOFFSET" }, 203 { R200_SE_VPORT_ZSCALE, "R200_SE_VPORT_ZSCALE" }, 204 { R200_SE_VPORT_ZOFFSET, "R200_SE_VPORT_ZOFFSET" }, 205 { R200_SE_ZBIAS_FACTOR, "R200_SE_ZBIAS_FACTOR" }, 206 { R200_SE_ZBIAS_CONSTANT, "R200_SE_ZBIAS_CONSTANT" }, 207 { R200_SE_LINE_WIDTH, "R200_SE_LINE_WIDTH" }, 208 { R200_SE_VAP_CNTL, "R200_SE_VAP_CNTL" }, 209 { R200_SE_VF_CNTL, "R200_SE_VF_CNTL" }, 210 { R200_SE_VTX_FMT_0, "R200_SE_VTX_FMT_0" }, 211 { R200_SE_VTX_FMT_1, "R200_SE_VTX_FMT_1" }, 212 { R200_SE_TCL_OUTPUT_VTX_FMT_0, "R200_SE_TCL_OUTPUT_VTX_FMT_0" }, 213 { R200_SE_TCL_OUTPUT_VTX_FMT_1, "R200_SE_TCL_OUTPUT_VTX_FMT_1" }, 214 { R200_SE_VTE_CNTL, "R200_SE_VTE_CNTL" }, 215 { R200_SE_VTX_NUM_ARRAYS, "R200_SE_VTX_NUM_ARRAYS" }, 216 { R200_SE_VTX_AOS_ATTR01, "R200_SE_VTX_AOS_ATTR01" }, 217 { R200_SE_VTX_AOS_ADDR0, "R200_SE_VTX_AOS_ADDR0" }, 218 { R200_SE_VTX_AOS_ADDR1, "R200_SE_VTX_AOS_ADDR1" }, 219 { R200_SE_VTX_AOS_ATTR23, "R200_SE_VTX_AOS_ATTR23" }, 220 { R200_SE_VTX_AOS_ADDR2, "R200_SE_VTX_AOS_ADDR2" }, 221 { R200_SE_VTX_AOS_ADDR3, "R200_SE_VTX_AOS_ADDR3" }, 222 { R200_SE_VTX_AOS_ATTR45, "R200_SE_VTX_AOS_ATTR45" }, 223 { R200_SE_VTX_AOS_ADDR4, "R200_SE_VTX_AOS_ADDR4" }, 224 { R200_SE_VTX_AOS_ADDR5, "R200_SE_VTX_AOS_ADDR5" }, 225 { R200_SE_VTX_AOS_ATTR67, "R200_SE_VTX_AOS_ATTR67" }, 226 { R200_SE_VTX_AOS_ADDR6, "R200_SE_VTX_AOS_ADDR6" }, 227 { R200_SE_VTX_AOS_ADDR7, "R200_SE_VTX_AOS_ADDR7" }, 228 { R200_SE_VTX_AOS_ATTR89, "R200_SE_VTX_AOS_ATTR89" }, 229 { R200_SE_VTX_AOS_ADDR8, "R200_SE_VTX_AOS_ADDR8" }, 230 { R200_SE_VTX_AOS_ADDR9, "R200_SE_VTX_AOS_ADDR9" }, 231 { R200_SE_VTX_AOS_ATTR1011, "R200_SE_VTX_AOS_ATTR1011" }, 232 { R200_SE_VTX_AOS_ADDR10, "R200_SE_VTX_AOS_ADDR10" }, 233 { R200_SE_VTX_AOS_ADDR11, "R200_SE_VTX_AOS_ADDR11" }, 234 { R200_SE_VF_MAX_VTX_INDX, "R200_SE_VF_MAX_VTX_INDX" }, 235 { R200_SE_VF_MIN_VTX_INDX, "R200_SE_VF_MIN_VTX_INDX" }, 236 { R200_SE_VTX_STATE_CNTL, "R200_SE_VTX_STATE_CNTL" }, 237 { R200_SE_TCL_VECTOR_INDX_REG, "R200_SE_TCL_VECTOR_INDX_REG" }, 238 { R200_SE_TCL_VECTOR_DATA_REG, "R200_SE_TCL_VECTOR_DATA_REG" }, 239 { R200_SE_TCL_SCALAR_INDX_REG, "R200_SE_TCL_SCALAR_INDX_REG" }, 240 { R200_SE_TCL_SCALAR_DATA_REG, "R200_SE_TCL_SCALAR_DATA_REG" }, 241 { R200_SE_TCL_MATRIX_SEL_0, "R200_SE_TCL_MATRIX_SEL_0" }, 242 { R200_SE_TCL_MATRIX_SEL_1, "R200_SE_TCL_MATRIX_SEL_1" }, 243 { R200_SE_TCL_MATRIX_SEL_2, "R200_SE_TCL_MATRIX_SEL_2" }, 244 { R200_SE_TCL_MATRIX_SEL_3, "R200_SE_TCL_MATRIX_SEL_3" }, 245 { R200_SE_TCL_MATRIX_SEL_4, "R200_SE_TCL_MATRIX_SEL_4" }, 246 { R200_SE_TCL_LIGHT_MODEL_CTL_0, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, 247 { R200_SE_TCL_LIGHT_MODEL_CTL_1, "R200_SE_TCL_LIGHT_MODEL_CTL_1" }, 248 { R200_SE_TCL_PER_LIGHT_CTL_0, "R200_SE_TCL_PER_LIGHT_CTL_0" }, 249 { R200_SE_TCL_PER_LIGHT_CTL_1, "R200_SE_TCL_PER_LIGHT_CTL_1" }, 250 { R200_SE_TCL_PER_LIGHT_CTL_2, "R200_SE_TCL_PER_LIGHT_CTL_2" }, 251 { R200_SE_TCL_PER_LIGHT_CTL_3, "R200_SE_TCL_PER_LIGHT_CTL_3" }, 252 { R200_SE_TCL_TEX_PROC_CTL_2, "R200_SE_TCL_TEX_PROC_CTL_2" }, 253 { R200_SE_TCL_TEX_PROC_CTL_3, "R200_SE_TCL_TEX_PROC_CTL_3" }, 254 { R200_SE_TCL_TEX_PROC_CTL_0, "R200_SE_TCL_TEX_PROC_CTL_0" }, 255 { R200_SE_TCL_TEX_PROC_CTL_1, "R200_SE_TCL_TEX_PROC_CTL_1" }, 256 { R200_SE_TC_TEX_CYL_WRAP_CTL, "R200_SE_TC_TEX_CYL_WRAP_CTL" }, 257 { R200_SE_TCL_UCP_VERT_BLEND_CTL, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, 258 { R200_SE_TCL_POINT_SPRITE_CNTL, "R200_SE_TCL_POINT_SPRITE_CNTL" }, 259 { R200_SE_VTX_ST_POS_0_X_4, "R200_SE_VTX_ST_POS_0_X_4" }, 260 { R200_SE_VTX_ST_POS_0_Y_4, "R200_SE_VTX_ST_POS_0_Y_4" }, 261 { R200_SE_VTX_ST_POS_0_Z_4, "R200_SE_VTX_ST_POS_0_Z_4" }, 262 { R200_SE_VTX_ST_POS_0_W_4, "R200_SE_VTX_ST_POS_0_W_4" }, 263 { R200_SE_VTX_ST_NORM_0_X, "R200_SE_VTX_ST_NORM_0_X" }, 264 { R200_SE_VTX_ST_NORM_0_Y, "R200_SE_VTX_ST_NORM_0_Y" }, 265 { R200_SE_VTX_ST_NORM_0_Z, "R200_SE_VTX_ST_NORM_0_Z" }, 266 { R200_SE_VTX_ST_PVMS, "R200_SE_VTX_ST_PVMS" }, 267 { R200_SE_VTX_ST_CLR_0_R, "R200_SE_VTX_ST_CLR_0_R" }, 268 { R200_SE_VTX_ST_CLR_0_G, "R200_SE_VTX_ST_CLR_0_G" }, 269 { R200_SE_VTX_ST_CLR_0_B, "R200_SE_VTX_ST_CLR_0_B" }, 270 { R200_SE_VTX_ST_CLR_0_A, "R200_SE_VTX_ST_CLR_0_A" }, 271 { R200_SE_VTX_ST_CLR_1_R, "R200_SE_VTX_ST_CLR_1_R" }, 272 { R200_SE_VTX_ST_CLR_1_G, "R200_SE_VTX_ST_CLR_1_G" }, 273 { R200_SE_VTX_ST_CLR_1_B, "R200_SE_VTX_ST_CLR_1_B" }, 274 { R200_SE_VTX_ST_CLR_1_A, "R200_SE_VTX_ST_CLR_1_A" }, 275 { R200_SE_VTX_ST_CLR_2_R, "R200_SE_VTX_ST_CLR_2_R" }, 276 { R200_SE_VTX_ST_CLR_2_G, "R200_SE_VTX_ST_CLR_2_G" }, 277 { R200_SE_VTX_ST_CLR_2_B, "R200_SE_VTX_ST_CLR_2_B" }, 278 { R200_SE_VTX_ST_CLR_2_A, "R200_SE_VTX_ST_CLR_2_A" }, 279 { R200_SE_VTX_ST_CLR_3_R, "R200_SE_VTX_ST_CLR_3_R" }, 280 { R200_SE_VTX_ST_CLR_3_G, "R200_SE_VTX_ST_CLR_3_G" }, 281 { R200_SE_VTX_ST_CLR_3_B, "R200_SE_VTX_ST_CLR_3_B" }, 282 { R200_SE_VTX_ST_CLR_3_A, "R200_SE_VTX_ST_CLR_3_A" }, 283 { R200_SE_VTX_ST_CLR_4_R, "R200_SE_VTX_ST_CLR_4_R" }, 284 { R200_SE_VTX_ST_CLR_4_G, "R200_SE_VTX_ST_CLR_4_G" }, 285 { R200_SE_VTX_ST_CLR_4_B, "R200_SE_VTX_ST_CLR_4_B" }, 286 { R200_SE_VTX_ST_CLR_4_A, "R200_SE_VTX_ST_CLR_4_A" }, 287 { R200_SE_VTX_ST_CLR_5_R, "R200_SE_VTX_ST_CLR_5_R" }, 288 { R200_SE_VTX_ST_CLR_5_G, "R200_SE_VTX_ST_CLR_5_G" }, 289 { R200_SE_VTX_ST_CLR_5_B, "R200_SE_VTX_ST_CLR_5_B" }, 290 { R200_SE_VTX_ST_CLR_5_A, "R200_SE_VTX_ST_CLR_5_A" }, 291 { R200_SE_VTX_ST_CLR_6_R, "R200_SE_VTX_ST_CLR_6_R" }, 292 { R200_SE_VTX_ST_CLR_6_G, "R200_SE_VTX_ST_CLR_6_G" }, 293 { R200_SE_VTX_ST_CLR_6_B, "R200_SE_VTX_ST_CLR_6_B" }, 294 { R200_SE_VTX_ST_CLR_6_A, "R200_SE_VTX_ST_CLR_6_A" }, 295 { R200_SE_VTX_ST_CLR_7_R, "R200_SE_VTX_ST_CLR_7_R" }, 296 { R200_SE_VTX_ST_CLR_7_G, "R200_SE_VTX_ST_CLR_7_G" }, 297 { R200_SE_VTX_ST_CLR_7_B, "R200_SE_VTX_ST_CLR_7_B" }, 298 { R200_SE_VTX_ST_CLR_7_A, "R200_SE_VTX_ST_CLR_7_A" }, 299 { R200_SE_VTX_ST_TEX_0_S, "R200_SE_VTX_ST_TEX_0_S" }, 300 { R200_SE_VTX_ST_TEX_0_T, "R200_SE_VTX_ST_TEX_0_T" }, 301 { R200_SE_VTX_ST_TEX_0_R, "R200_SE_VTX_ST_TEX_0_R" }, 302 { R200_SE_VTX_ST_TEX_0_Q, "R200_SE_VTX_ST_TEX_0_Q" }, 303 { R200_SE_VTX_ST_TEX_1_S, "R200_SE_VTX_ST_TEX_1_S" }, 304 { R200_SE_VTX_ST_TEX_1_T, "R200_SE_VTX_ST_TEX_1_T" }, 305 { R200_SE_VTX_ST_TEX_1_R, "R200_SE_VTX_ST_TEX_1_R" }, 306 { R200_SE_VTX_ST_TEX_1_Q, "R200_SE_VTX_ST_TEX_1_Q" }, 307 { R200_SE_VTX_ST_TEX_2_S, "R200_SE_VTX_ST_TEX_2_S" }, 308 { R200_SE_VTX_ST_TEX_2_T, "R200_SE_VTX_ST_TEX_2_T" }, 309 { R200_SE_VTX_ST_TEX_2_R, "R200_SE_VTX_ST_TEX_2_R" }, 310 { R200_SE_VTX_ST_TEX_2_Q, "R200_SE_VTX_ST_TEX_2_Q" }, 311 { R200_SE_VTX_ST_TEX_3_S, "R200_SE_VTX_ST_TEX_3_S" }, 312 { R200_SE_VTX_ST_TEX_3_T, "R200_SE_VTX_ST_TEX_3_T" }, 313 { R200_SE_VTX_ST_TEX_3_R, "R200_SE_VTX_ST_TEX_3_R" }, 314 { R200_SE_VTX_ST_TEX_3_Q, "R200_SE_VTX_ST_TEX_3_Q" }, 315 { R200_SE_VTX_ST_TEX_4_S, "R200_SE_VTX_ST_TEX_4_S" }, 316 { R200_SE_VTX_ST_TEX_4_T, "R200_SE_VTX_ST_TEX_4_T" }, 317 { R200_SE_VTX_ST_TEX_4_R, "R200_SE_VTX_ST_TEX_4_R" }, 318 { R200_SE_VTX_ST_TEX_4_Q, "R200_SE_VTX_ST_TEX_4_Q" }, 319 { R200_SE_VTX_ST_TEX_5_S, "R200_SE_VTX_ST_TEX_5_S" }, 320 { R200_SE_VTX_ST_TEX_5_T, "R200_SE_VTX_ST_TEX_5_T" }, 321 { R200_SE_VTX_ST_TEX_5_R, "R200_SE_VTX_ST_TEX_5_R" }, 322 { R200_SE_VTX_ST_TEX_5_Q, "R200_SE_VTX_ST_TEX_5_Q" }, 323 { R200_SE_VTX_ST_PNT_SPRT_SZ, "R200_SE_VTX_ST_PNT_SPRT_SZ" }, 324 { R200_SE_VTX_ST_DISC_FOG, "R200_SE_VTX_ST_DISC_FOG" }, 325 { R200_SE_VTX_ST_SHININESS_0, "R200_SE_VTX_ST_SHININESS_0" }, 326 { R200_SE_VTX_ST_SHININESS_1, "R200_SE_VTX_ST_SHININESS_1" }, 327 { R200_SE_VTX_ST_BLND_WT_0, "R200_SE_VTX_ST_BLND_WT_0" }, 328 { R200_SE_VTX_ST_BLND_WT_1, "R200_SE_VTX_ST_BLND_WT_1" }, 329 { R200_SE_VTX_ST_BLND_WT_2, "R200_SE_VTX_ST_BLND_WT_2" }, 330 { R200_SE_VTX_ST_BLND_WT_3, "R200_SE_VTX_ST_BLND_WT_3" }, 331 { R200_SE_VTX_ST_POS_1_X, "R200_SE_VTX_ST_POS_1_X" }, 332 { R200_SE_VTX_ST_POS_1_Y, "R200_SE_VTX_ST_POS_1_Y" }, 333 { R200_SE_VTX_ST_POS_1_Z, "R200_SE_VTX_ST_POS_1_Z" }, 334 { R200_SE_VTX_ST_POS_1_W, "R200_SE_VTX_ST_POS_1_W" }, 335 { R200_SE_VTX_ST_NORM_1_X, "R200_SE_VTX_ST_NORM_1_X" }, 336 { R200_SE_VTX_ST_NORM_1_Y, "R200_SE_VTX_ST_NORM_1_Y" }, 337 { R200_SE_VTX_ST_NORM_1_Z, "R200_SE_VTX_ST_NORM_1_Z" }, 338 { R200_SE_VTX_ST_USR_CLR_0_R, "R200_SE_VTX_ST_USR_CLR_0_R" }, 339 { R200_SE_VTX_ST_USR_CLR_0_G, "R200_SE_VTX_ST_USR_CLR_0_G" }, 340 { R200_SE_VTX_ST_USR_CLR_0_B, "R200_SE_VTX_ST_USR_CLR_0_B" }, 341 { R200_SE_VTX_ST_USR_CLR_0_A, "R200_SE_VTX_ST_USR_CLR_0_A" }, 342 { R200_SE_VTX_ST_USR_CLR_1_R, "R200_SE_VTX_ST_USR_CLR_1_R" }, 343 { R200_SE_VTX_ST_USR_CLR_1_G, "R200_SE_VTX_ST_USR_CLR_1_G" }, 344 { R200_SE_VTX_ST_USR_CLR_1_B, "R200_SE_VTX_ST_USR_CLR_1_B" }, 345 { R200_SE_VTX_ST_USR_CLR_1_A, "R200_SE_VTX_ST_USR_CLR_1_A" }, 346 { R200_SE_VTX_ST_CLR_0_PKD, "R200_SE_VTX_ST_CLR_0_PKD" }, 347 { R200_SE_VTX_ST_CLR_1_PKD, "R200_SE_VTX_ST_CLR_1_PKD" }, 348 { R200_SE_VTX_ST_CLR_2_PKD, "R200_SE_VTX_ST_CLR_2_PKD" }, 349 { R200_SE_VTX_ST_CLR_3_PKD, "R200_SE_VTX_ST_CLR_3_PKD" }, 350 { R200_SE_VTX_ST_CLR_4_PKD, "R200_SE_VTX_ST_CLR_4_PKD" }, 351 { R200_SE_VTX_ST_CLR_5_PKD, "R200_SE_VTX_ST_CLR_5_PKD" }, 352 { R200_SE_VTX_ST_CLR_6_PKD, "R200_SE_VTX_ST_CLR_6_PKD" }, 353 { R200_SE_VTX_ST_CLR_7_PKD, "R200_SE_VTX_ST_CLR_7_PKD" }, 354 { R200_SE_VTX_ST_POS_0_X_2, "R200_SE_VTX_ST_POS_0_X_2" }, 355 { R200_SE_VTX_ST_POS_0_Y_2, "R200_SE_VTX_ST_POS_0_Y_2" }, 356 { R200_SE_VTX_ST_PAR_CLR_LD, "R200_SE_VTX_ST_PAR_CLR_LD" }, 357 { R200_SE_VTX_ST_USR_CLR_PKD, "R200_SE_VTX_ST_USR_CLR_PKD" }, 358 { R200_SE_VTX_ST_POS_0_X_3, "R200_SE_VTX_ST_POS_0_X_3" }, 359 { R200_SE_VTX_ST_POS_0_Y_3, "R200_SE_VTX_ST_POS_0_Y_3" }, 360 { R200_SE_VTX_ST_POS_0_Z_3, "R200_SE_VTX_ST_POS_0_Z_3" }, 361 { R200_SE_VTX_ST_END_OF_PKT, "R200_SE_VTX_ST_END_OF_PKT" }, 362 { R200_RE_POINTSIZE, "R200_RE_POINTSIZE" }, 363 { R200_RE_TOP_LEFT, "R200_RE_TOP_LEFT" }, 364 { R200_RE_AUX_SCISSOR_CNTL, "R200_RE_AUX_SCISSOR_CNTL" }, 365 { R200_PP_TXFILTER_0, "R200_PP_TXFILTER_0" }, 366 { R200_PP_TXFORMAT_0, "R200_PP_TXFORMAT_0" }, 367 { R200_PP_TXSIZE_0, "R200_PP_TXSIZE_0" }, 368 { R200_PP_TXFORMAT_X_0, "R200_PP_TXFORMAT_X_0" }, 369 { R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" }, 370 { R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" }, 371 { R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" }, 372 { R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" }, 373 { R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" }, 374 { R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" }, 375 { R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" }, 376 { R200_PP_TXFORMAT_X_1, "R200_PP_TXFORMAT_X_1" }, 377 { R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" }, 378 { R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" }, 379 { R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" }, 380 { R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" }, 381 { R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" }, 382 { R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" }, 383 { R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" }, 384 { R200_PP_TXFORMAT_X_2, "R200_PP_TXFORMAT_X_2" }, 385 { R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" }, 386 { R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" }, 387 { R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" }, 388 { R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" }, 389 { R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" }, 390 { R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" }, 391 { R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" }, 392 { R200_PP_TXFORMAT_X_3, "R200_PP_TXFORMAT_X_3" }, 393 { R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" }, 394 { R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" }, 395 { R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" }, 396 { R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" }, 397 { R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" }, 398 { R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" }, 399 { R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" }, 400 { R200_PP_TXFORMAT_X_4, "R200_PP_TXFORMAT_X_4" }, 401 { R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" }, 402 { R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" }, 403 { R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" }, 404 { R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" }, 405 { R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" }, 406 { R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" }, 407 { R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" }, 408 { R200_PP_TXFORMAT_X_5, "R200_PP_TXFORMAT_X_5" }, 409 { R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" }, 410 { R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" }, 411 { R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" }, 412 { R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" }, 413 { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" }, 414 { R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" }, 415 { R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" }, 416 { R200_PP_CUBIC_OFFSET_F3_0, "R200_PP_CUBIC_OFFSET_F3_0" }, 417 { R200_PP_CUBIC_OFFSET_F4_0, "R200_PP_CUBIC_OFFSET_F4_0" }, 418 { R200_PP_CUBIC_OFFSET_F5_0, "R200_PP_CUBIC_OFFSET_F5_0" }, 419 { R200_PP_TXOFFSET_1, "R200_PP_TXOFFSET_1" }, 420 { R200_PP_CUBIC_OFFSET_F1_1, "R200_PP_CUBIC_OFFSET_F1_1" }, 421 { R200_PP_CUBIC_OFFSET_F2_1, "R200_PP_CUBIC_OFFSET_F2_1" }, 422 { R200_PP_CUBIC_OFFSET_F3_1, "R200_PP_CUBIC_OFFSET_F3_1" }, 423 { R200_PP_CUBIC_OFFSET_F4_1, "R200_PP_CUBIC_OFFSET_F4_1" }, 424 { R200_PP_CUBIC_OFFSET_F5_1, "R200_PP_CUBIC_OFFSET_F5_1" }, 425 { R200_PP_TXOFFSET_2, "R200_PP_TXOFFSET_2" }, 426 { R200_PP_CUBIC_OFFSET_F1_2, "R200_PP_CUBIC_OFFSET_F1_2" }, 427 { R200_PP_CUBIC_OFFSET_F2_2, "R200_PP_CUBIC_OFFSET_F2_2" }, 428 { R200_PP_CUBIC_OFFSET_F3_2, "R200_PP_CUBIC_OFFSET_F3_2" }, 429 { R200_PP_CUBIC_OFFSET_F4_2, "R200_PP_CUBIC_OFFSET_F4_2" }, 430 { R200_PP_CUBIC_OFFSET_F5_2, "R200_PP_CUBIC_OFFSET_F5_2" }, 431 { R200_PP_TXOFFSET_3, "R200_PP_TXOFFSET_3" }, 432 { R200_PP_CUBIC_OFFSET_F1_3, "R200_PP_CUBIC_OFFSET_F1_3" }, 433 { R200_PP_CUBIC_OFFSET_F2_3, "R200_PP_CUBIC_OFFSET_F2_3" }, 434 { R200_PP_CUBIC_OFFSET_F3_3, "R200_PP_CUBIC_OFFSET_F3_3" }, 435 { R200_PP_CUBIC_OFFSET_F4_3, "R200_PP_CUBIC_OFFSET_F4_3" }, 436 { R200_PP_CUBIC_OFFSET_F5_3, "R200_PP_CUBIC_OFFSET_F5_3" }, 437 { R200_PP_TXOFFSET_4, "R200_PP_TXOFFSET_4" }, 438 { R200_PP_CUBIC_OFFSET_F1_4, "R200_PP_CUBIC_OFFSET_F1_4" }, 439 { R200_PP_CUBIC_OFFSET_F2_4, "R200_PP_CUBIC_OFFSET_F2_4" }, 440 { R200_PP_CUBIC_OFFSET_F3_4, "R200_PP_CUBIC_OFFSET_F3_4" }, 441 { R200_PP_CUBIC_OFFSET_F4_4, "R200_PP_CUBIC_OFFSET_F4_4" }, 442 { R200_PP_CUBIC_OFFSET_F5_4, "R200_PP_CUBIC_OFFSET_F5_4" }, 443 { R200_PP_TXOFFSET_5, "R200_PP_TXOFFSET_5" }, 444 { R200_PP_CUBIC_OFFSET_F1_5, "R200_PP_CUBIC_OFFSET_F1_5" }, 445 { R200_PP_CUBIC_OFFSET_F2_5, "R200_PP_CUBIC_OFFSET_F2_5" }, 446 { R200_PP_CUBIC_OFFSET_F3_5, "R200_PP_CUBIC_OFFSET_F3_5" }, 447 { R200_PP_CUBIC_OFFSET_F4_5, "R200_PP_CUBIC_OFFSET_F4_5" }, 448 { R200_PP_CUBIC_OFFSET_F5_5, "R200_PP_CUBIC_OFFSET_F5_5" }, 449 { R200_PP_TAM_DEBUG3, "R200_PP_TAM_DEBUG3" }, 450 { R200_PP_TFACTOR_0, "R200_PP_TFACTOR_0" }, 451 { R200_PP_TFACTOR_1, "R200_PP_TFACTOR_1" }, 452 { R200_PP_TFACTOR_2, "R200_PP_TFACTOR_2" }, 453 { R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" }, 454 { R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" }, 455 { R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" }, 456 { R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" }, 457 { R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" }, 458 { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" }, 459 { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" }, 460 { R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" }, 461 { R200_PP_TXABLEND2_0, "R200_PP_TXABLEND2_0" }, 462 { R200_PP_TXCBLEND_1, "R200_PP_TXCBLEND_1" }, 463 { R200_PP_TXCBLEND2_1, "R200_PP_TXCBLEND2_1" }, 464 { R200_PP_TXABLEND_1, "R200_PP_TXABLEND_1" }, 465 { R200_PP_TXABLEND2_1, "R200_PP_TXABLEND2_1" }, 466 { R200_PP_TXCBLEND_2, "R200_PP_TXCBLEND_2" }, 467 { R200_PP_TXCBLEND2_2, "R200_PP_TXCBLEND2_2" }, 468 { R200_PP_TXABLEND_2, "R200_PP_TXABLEND_2" }, 469 { R200_PP_TXABLEND2_2, "R200_PP_TXABLEND2_2" }, 470 { R200_PP_TXCBLEND_3, "R200_PP_TXCBLEND_3" }, 471 { R200_PP_TXCBLEND2_3, "R200_PP_TXCBLEND2_3" }, 472 { R200_PP_TXABLEND_3, "R200_PP_TXABLEND_3" }, 473 { R200_PP_TXABLEND2_3, "R200_PP_TXABLEND2_3" }, 474 { R200_PP_TXCBLEND_4, "R200_PP_TXCBLEND_4" }, 475 { R200_PP_TXCBLEND2_4, "R200_PP_TXCBLEND2_4" }, 476 { R200_PP_TXABLEND_4, "R200_PP_TXABLEND_4" }, 477 { R200_PP_TXABLEND2_4, "R200_PP_TXABLEND2_4" }, 478 { R200_PP_TXCBLEND_5, "R200_PP_TXCBLEND_5" }, 479 { R200_PP_TXCBLEND2_5, "R200_PP_TXCBLEND2_5" }, 480 { R200_PP_TXABLEND_5, "R200_PP_TXABLEND_5" }, 481 { R200_PP_TXABLEND2_5, "R200_PP_TXABLEND2_5" }, 482 { R200_PP_TXCBLEND_6, "R200_PP_TXCBLEND_6" }, 483 { R200_PP_TXCBLEND2_6, "R200_PP_TXCBLEND2_6" }, 484 { R200_PP_TXABLEND_6, "R200_PP_TXABLEND_6" }, 485 { R200_PP_TXABLEND2_6, "R200_PP_TXABLEND2_6" }, 486 { R200_PP_TXCBLEND_7, "R200_PP_TXCBLEND_7" }, 487 { R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" }, 488 { R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" }, 489 { R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" }, 490 { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" }, 491 { R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" }, 492 { R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" }, 493 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, 494 { R200_PP_CNTL_X, "R200_PP_CNTL_X" }, 495 { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" }, 496 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, 497 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" }, 498 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" }, 499 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" }, 500 { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" }, 501 { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" }, 502 { R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" }, 503 { R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" }, 504 { R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" }, 505 { R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" }, 506 { R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" }, 507 { R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" }, 508 { R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" }, 509 { R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" }, 510 { R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" }, 511 { R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" }, 512 { R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" }, 513 { R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" }, 514 { R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" }, 515 { R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" }, 516 { R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" }, 517 { R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" }, 518 { R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" }, 519 { R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" }, 520 { R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" }, 521 { R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" }, 522 { R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" }, 523 { R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" }, 524 { R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" }, 525 { R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" }, 526 { R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" }, 527 { R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" }, 528 { R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" }, 529 { R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" }, 530 { R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" }, 531 { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" }, 532 { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" }, 533 { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" }, 534 { R200_VAP_PVS_CNTL_1, "R200_VAP_PVS_CNTL_1" }, 535 { R200_VAP_PVS_CNTL_2, "R200_VAP_PVS_CNTL_2" }, 536 }; 537 538 static struct reg_names scalar_names[] = { 539 { R200_SS_LIGHT_DCD_ADDR, "R200_SS_LIGHT_DCD_ADDR" }, 540 { R200_SS_LIGHT_DCM_ADDR, "R200_SS_LIGHT_DCM_ADDR" }, 541 { R200_SS_LIGHT_SPOT_EXPONENT_ADDR, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" }, 542 { R200_SS_LIGHT_SPOT_CUTOFF_ADDR, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" }, 543 { R200_SS_LIGHT_SPECULAR_THRESH_ADDR, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" }, 544 { R200_SS_LIGHT_RANGE_CUTOFF_SQRD, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" }, 545 { R200_SS_LIGHT_RANGE_ATT_CONST, "R200_SS_LIGHT_RANGE_ATT_CONST" }, 546 { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" }, 547 { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" }, 548 { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" }, 549 { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" }, 550 { R200_SS_MAT_0_SHININESS, "R200_SS_MAT_0_SHININESS" }, 551 { R200_SS_MAT_1_SHININESS, "R200_SS_MAT_1_SHININESS" }, 552 { 1000, "" }, 553 }; 554 555 /* Puff these out to make them look like normal (dword) registers. 556 */ 557 static struct reg_names vector_names[] = { 558 { 0, "start" }, 559 { R200_VS_LIGHT_AMBIENT_ADDR, "R200_VS_LIGHT_AMBIENT_ADDR" }, 560 { R200_VS_LIGHT_DIFFUSE_ADDR, "R200_VS_LIGHT_DIFFUSE_ADDR" }, 561 { R200_VS_LIGHT_SPECULAR_ADDR, "R200_VS_LIGHT_SPECULAR_ADDR" }, 562 { R200_VS_LIGHT_DIRPOS_ADDR, "R200_VS_LIGHT_DIRPOS_ADDR" }, 563 { R200_VS_LIGHT_HWVSPOT_ADDR, "R200_VS_LIGHT_HWVSPOT_ADDR" }, 564 { R200_VS_LIGHT_ATTENUATION_ADDR, "R200_VS_LIGHT_ATTENUATION_ADDR" }, 565 { R200_VS_SPOT_DUAL_CONE, "R200_VS_SPOT_DUAL_CONE" }, 566 { R200_VS_GLOBAL_AMBIENT_ADDR, "R200_VS_GLOBAL_AMBIENT_ADDR" }, 567 { R200_VS_FOG_PARAM_ADDR, "R200_VS_FOG_PARAM_ADDR" }, 568 { R200_VS_EYE_VECTOR_ADDR, "R200_VS_EYE_VECTOR_ADDR" }, 569 { R200_VS_UCP_ADDR, "R200_VS_UCP_ADDR" }, 570 { R200_VS_PNT_SPRITE_VPORT_SCALE, "R200_VS_PNT_SPRITE_VPORT_SCALE" }, 571 { R200_VS_MATRIX_0_MV, "R200_VS_MATRIX_0_MV" }, 572 { R200_VS_MATRIX_1_INV_MV, "R200_VS_MATRIX_1_INV_MV" }, 573 { R200_VS_MATRIX_2_MVP, "R200_VS_MATRIX_2_MVP" }, 574 { R200_VS_MATRIX_3_TEX0, "R200_VS_MATRIX_3_TEX0" }, 575 { R200_VS_MATRIX_4_TEX1, "R200_VS_MATRIX_4_TEX1" }, 576 { R200_VS_MATRIX_5_TEX2, "R200_VS_MATRIX_5_TEX2" }, 577 { R200_VS_MATRIX_6_TEX3, "R200_VS_MATRIX_6_TEX3" }, 578 { R200_VS_MATRIX_7_TEX4, "R200_VS_MATRIX_7_TEX4" }, 579 { R200_VS_MATRIX_8_TEX5, "R200_VS_MATRIX_8_TEX5" }, 580 { R200_VS_MAT_0_EMISS, "R200_VS_MAT_0_EMISS" }, 581 { R200_VS_MAT_0_AMB, "R200_VS_MAT_0_AMB" }, 582 { R200_VS_MAT_0_DIF, "R200_VS_MAT_0_DIF" }, 583 { R200_VS_MAT_0_SPEC, "R200_VS_MAT_0_SPEC" }, 584 { R200_VS_MAT_1_EMISS, "R200_VS_MAT_1_EMISS" }, 585 { R200_VS_MAT_1_AMB, "R200_VS_MAT_1_AMB" }, 586 { R200_VS_MAT_1_DIF, "R200_VS_MAT_1_DIF" }, 587 { R200_VS_MAT_1_SPEC, "R200_VS_MAT_1_SPEC" }, 588 { R200_VS_EYE2CLIP_MTX, "R200_VS_EYE2CLIP_MTX" }, 589 { R200_VS_PNT_SPRITE_ATT_CONST, "R200_VS_PNT_SPRITE_ATT_CONST" }, 590 { R200_VS_PNT_SPRITE_EYE_IN_MODEL, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" }, 591 { R200_VS_PNT_SPRITE_CLAMP, "R200_VS_PNT_SPRITE_CLAMP" }, 592 { R200_VS_MAX, "R200_VS_MAX" }, 593 { 1000, "" }, 594 }; 595 596 union fi { float f; int i; }; 597 598 #define ISVEC 1 599 #define ISFLOAT 2 600 #define TOUCHED 4 601 602 struct reg { 603 int idx; 604 struct reg_names *closest; 605 int flags; 606 union fi current; 607 union fi *values; 608 int nvalues; 609 int nalloc; 610 float vmin, vmax; 611 }; 612 613 614 static struct reg regs[Elements(reg_names)+1]; 615 static struct reg scalars[512+1]; 616 static struct reg vectors[512*4+1]; 617 618 static int total, total_changed, bufs; 619 620 static void init_regs( void ) 621 { 622 struct reg_names *tmp; 623 int i; 624 625 for (i = 0 ; i < Elements(regs) ; i++) { 626 regs[i].idx = reg_names[i].idx; 627 regs[i].closest = ®_names[i]; 628 regs[i].flags = 0; 629 } 630 631 for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) { 632 if (tmp[1].idx == i) tmp++; 633 scalars[i].idx = i; 634 scalars[i].closest = tmp; 635 scalars[i].flags = ISFLOAT; 636 } 637 638 for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) { 639 if (tmp[1].idx*4 == i) tmp++; 640 vectors[i].idx = i; 641 vectors[i].closest = tmp; 642 vectors[i].flags = ISFLOAT|ISVEC; 643 } 644 645 regs[Elements(regs)-1].idx = -1; 646 scalars[Elements(scalars)-1].idx = -1; 647 vectors[Elements(vectors)-1].idx = -1; 648 } 649 650 static int find_or_add_value( struct reg *reg, int val ) 651 { 652 int j; 653 654 for ( j = 0 ; j < reg->nvalues ; j++) 655 if ( val == reg->values[j].i ) 656 return 1; 657 658 if (j == reg->nalloc) { 659 reg->nalloc += 5; 660 reg->nalloc *= 2; 661 reg->values = (union fi *) realloc( reg->values, 662 reg->nalloc * sizeof(union fi) ); 663 } 664 665 reg->values[reg->nvalues++].i = val; 666 return 0; 667 } 668 669 static struct reg *lookup_reg( struct reg *tab, int reg ) 670 { 671 int i; 672 673 for (i = 0 ; tab[i].idx != -1 ; i++) { 674 if (tab[i].idx == reg) 675 return &tab[i]; 676 } 677 678 fprintf(stderr, "*** unknown reg 0x%x\n", reg); 679 return NULL; 680 } 681 682 683 static const char *get_reg_name( struct reg *reg ) 684 { 685 static char tmp[80]; 686 687 if (reg->idx == reg->closest->idx) 688 return reg->closest->name; 689 690 691 if (reg->flags & ISVEC) { 692 if (reg->idx/4 != reg->closest->idx) 693 sprintf(tmp, "%s+%d[%d]", 694 reg->closest->name, 695 (reg->idx/4) - reg->closest->idx, 696 reg->idx%4); 697 else 698 sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4); 699 } 700 else { 701 if (reg->idx != reg->closest->idx) 702 sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx); 703 else 704 sprintf(tmp, "%s", reg->closest->name); 705 } 706 707 return tmp; 708 } 709 710 static int print_int_reg_assignment( struct reg *reg, int data ) 711 { 712 int changed = (reg->current.i != data); 713 int ever_seen = find_or_add_value( reg, data ); 714 715 if (VERBOSE || (NORMAL && (changed || !ever_seen))) 716 fprintf(stderr, " %s <-- 0x%x", get_reg_name(reg), data); 717 718 if (NORMAL) { 719 if (!ever_seen) 720 fprintf(stderr, " *** BRAND NEW VALUE"); 721 else if (changed) 722 fprintf(stderr, " *** CHANGED"); 723 } 724 725 reg->current.i = data; 726 727 if (VERBOSE || (NORMAL && (changed || !ever_seen))) 728 fprintf(stderr, "\n"); 729 730 return changed; 731 } 732 733 734 static int print_float_reg_assignment( struct reg *reg, float data ) 735 { 736 int changed = (reg->current.f != data); 737 int newmin = (data < reg->vmin); 738 int newmax = (data > reg->vmax); 739 740 if (VERBOSE || (NORMAL && (newmin || newmax || changed))) 741 fprintf(stderr, " %s <-- %.3f", get_reg_name(reg), data); 742 743 if (NORMAL) { 744 if (newmin) { 745 fprintf(stderr, " *** NEW MIN (prev %.3f)", reg->vmin); 746 reg->vmin = data; 747 } 748 else if (newmax) { 749 fprintf(stderr, " *** NEW MAX (prev %.3f)", reg->vmax); 750 reg->vmax = data; 751 } 752 else if (changed) { 753 fprintf(stderr, " *** CHANGED"); 754 } 755 } 756 757 reg->current.f = data; 758 759 if (VERBOSE || (NORMAL && (newmin || newmax || changed))) 760 fprintf(stderr, "\n"); 761 762 return changed; 763 } 764 765 static int print_reg_assignment( struct reg *reg, int data ) 766 { 767 float_ui32_type datau; 768 datau.ui32 = data; 769 reg->flags |= TOUCHED; 770 if (reg->flags & ISFLOAT) 771 return print_float_reg_assignment( reg, datau.f ); 772 else 773 return print_int_reg_assignment( reg, data ); 774 } 775 776 static void print_reg( struct reg *reg ) 777 { 778 if (reg->flags & TOUCHED) { 779 if (reg->flags & ISFLOAT) { 780 fprintf(stderr, " %s == %f\n", get_reg_name(reg), reg->current.f); 781 } else { 782 fprintf(stderr, " %s == 0x%x\n", get_reg_name(reg), reg->current.i); 783 } 784 } 785 } 786 787 788 static void dump_state( void ) 789 { 790 int i; 791 792 for (i = 0 ; i < Elements(regs) ; i++) 793 print_reg( ®s[i] ); 794 795 for (i = 0 ; i < Elements(scalars) ; i++) 796 print_reg( &scalars[i] ); 797 798 for (i = 0 ; i < Elements(vectors) ; i++) 799 print_reg( &vectors[i] ); 800 } 801 802 803 804 static int radeon_emit_packets( 805 drm_radeon_cmd_header_t header, 806 drm_radeon_cmd_buffer_t *cmdbuf ) 807 { 808 int id = (int)header.packet.packet_id; 809 int sz = packet[id].len; 810 int *data = (int *)cmdbuf->buf; 811 int i; 812 813 if (sz * sizeof(int) > cmdbuf->bufsz) { 814 fprintf(stderr, "Packet overflows cmdbuf\n"); 815 return -EINVAL; 816 } 817 818 if (!packet[id].name) { 819 fprintf(stderr, "*** Unknown packet 0 nr %d\n", id ); 820 return -EINVAL; 821 } 822 823 824 if (VERBOSE) 825 fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz ); 826 827 for ( i = 0 ; i < sz ; i++) { 828 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); 829 if (print_reg_assignment( reg, data[i] )) 830 total_changed++; 831 total++; 832 } 833 834 cmdbuf->buf += sz * sizeof(int); 835 cmdbuf->bufsz -= sz * sizeof(int); 836 return 0; 837 } 838 839 840 static int radeon_emit_scalars( 841 drm_radeon_cmd_header_t header, 842 drm_radeon_cmd_buffer_t *cmdbuf ) 843 { 844 int sz = header.scalars.count; 845 int *data = (int *)cmdbuf->buf; 846 int start = header.scalars.offset; 847 int stride = header.scalars.stride; 848 int i; 849 850 if (VERBOSE) 851 fprintf(stderr, "emit scalars, start %d stride %d nr %d (end %d)\n", 852 start, stride, sz, start + stride * sz); 853 854 855 for (i = 0 ; i < sz ; i++, start += stride) { 856 struct reg *reg = lookup_reg( scalars, start ); 857 if (print_reg_assignment( reg, data[i] )) 858 total_changed++; 859 total++; 860 } 861 862 cmdbuf->buf += sz * sizeof(int); 863 cmdbuf->bufsz -= sz * sizeof(int); 864 return 0; 865 } 866 867 868 static int radeon_emit_scalars2( 869 drm_radeon_cmd_header_t header, 870 drm_radeon_cmd_buffer_t *cmdbuf ) 871 { 872 int sz = header.scalars.count; 873 int *data = (int *)cmdbuf->buf; 874 int start = header.scalars.offset + 0x100; 875 int stride = header.scalars.stride; 876 int i; 877 878 if (VERBOSE) 879 fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n", 880 start, stride, sz, start + stride * sz); 881 882 if (start + stride * sz > 258) { 883 fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz); 884 return -1; 885 } 886 887 for (i = 0 ; i < sz ; i++, start += stride) { 888 struct reg *reg = lookup_reg( scalars, start ); 889 if (print_reg_assignment( reg, data[i] )) 890 total_changed++; 891 total++; 892 } 893 894 cmdbuf->buf += sz * sizeof(int); 895 cmdbuf->bufsz -= sz * sizeof(int); 896 return 0; 897 } 898 899 /* Check: inf/nan/extreme-size? 900 * Check: table start, end, nr, etc. 901 */ 902 static int radeon_emit_vectors( 903 drm_radeon_cmd_header_t header, 904 drm_radeon_cmd_buffer_t *cmdbuf ) 905 { 906 int sz = header.vectors.count; 907 int *data = (int *)cmdbuf->buf; 908 int start = header.vectors.offset; 909 int stride = header.vectors.stride; 910 int i,j; 911 912 if (VERBOSE) 913 fprintf(stderr, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n", 914 start, stride, sz, start + stride * sz, header.i); 915 916 /* if (start + stride * (sz/4) > 128) { */ 917 /* fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */ 918 /* return -1; */ 919 /* } */ 920 921 for (i = 0 ; i < sz ; start += stride) { 922 int changed = 0; 923 for (j = 0 ; j < 4 ; i++,j++) { 924 struct reg *reg = lookup_reg( vectors, start*4+j ); 925 if (print_reg_assignment( reg, data[i] )) 926 changed = 1; 927 } 928 if (changed) 929 total_changed += 4; 930 total += 4; 931 } 932 933 934 cmdbuf->buf += sz * sizeof(int); 935 cmdbuf->bufsz -= sz * sizeof(int); 936 return 0; 937 } 938 939 static int radeon_emit_veclinear( 940 drm_radeon_cmd_header_t header, 941 drm_radeon_cmd_buffer_t *cmdbuf ) 942 { 943 int sz = header.veclinear.count * 4; 944 int *data = (int *)cmdbuf->buf; 945 float *fdata =(float *)cmdbuf->buf; 946 int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8); 947 int i; 948 949 if (1||VERBOSE) 950 fprintf(stderr, "emit vectors linear, start %d nr %d (end %d) (0x%x)\n", 951 start, sz >> 2, start + (sz >> 2), header.i); 952 953 954 if (start < 0x60) { 955 for (i = 0 ; i < sz ; i += 4) { 956 fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start, fdata[i]); 957 fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start, fdata[i+1]); 958 fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start, fdata[i+2]); 959 fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start, fdata[i+3]); 960 } 961 } 962 else if ((start >= 0x100) && (start < 0x160)) { 963 for (i = 0 ; i < sz ; i += 4) { 964 fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i]); 965 fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+1]); 966 fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+2]); 967 fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+3]); 968 } 969 } 970 else if ((start >= 0x80) && (start < 0xc0)) { 971 for (i = 0 ; i < sz ; i += 4) { 972 fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x80, data[i]); 973 fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x80, data[i+1]); 974 fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x80, data[i+2]); 975 fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x80, data[i+3]); 976 } 977 } 978 else if ((start >= 0x180) && (start < 0x1c0)) { 979 for (i = 0 ; i < sz ; i += 4) { 980 fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i]); 981 fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+1]); 982 fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+2]); 983 fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+3]); 984 } 985 } 986 else { 987 fprintf(stderr, "write to unknown vector area\n"); 988 } 989 990 cmdbuf->buf += sz * sizeof(int); 991 cmdbuf->bufsz -= sz * sizeof(int); 992 return 0; 993 } 994 995 #if 0 996 static int print_vertex_format( int vfmt ) 997 { 998 if (NORMAL) { 999 fprintf(stderr, " %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 1000 "vertex format", 1001 vfmt, 1002 "xy,", 1003 (vfmt & R200_VTX_Z0) ? "z," : "", 1004 (vfmt & R200_VTX_W0) ? "w0," : "", 1005 (vfmt & R200_VTX_FPCOLOR) ? "fpcolor," : "", 1006 (vfmt & R200_VTX_FPALPHA) ? "fpalpha," : "", 1007 (vfmt & R200_VTX_PKCOLOR) ? "pkcolor," : "", 1008 (vfmt & R200_VTX_FPSPEC) ? "fpspec," : "", 1009 (vfmt & R200_VTX_FPFOG) ? "fpfog," : "", 1010 (vfmt & R200_VTX_PKSPEC) ? "pkspec," : "", 1011 (vfmt & R200_VTX_ST0) ? "st0," : "", 1012 (vfmt & R200_VTX_ST1) ? "st1," : "", 1013 (vfmt & R200_VTX_Q1) ? "q1," : "", 1014 (vfmt & R200_VTX_ST2) ? "st2," : "", 1015 (vfmt & R200_VTX_Q2) ? "q2," : "", 1016 (vfmt & R200_VTX_ST3) ? "st3," : "", 1017 (vfmt & R200_VTX_Q3) ? "q3," : "", 1018 (vfmt & R200_VTX_Q0) ? "q0," : "", 1019 (vfmt & R200_VTX_N0) ? "n0," : "", 1020 (vfmt & R200_VTX_XY1) ? "xy1," : "", 1021 (vfmt & R200_VTX_Z1) ? "z1," : "", 1022 (vfmt & R200_VTX_W1) ? "w1," : "", 1023 (vfmt & R200_VTX_N1) ? "n1," : ""); 1024 1025 1026 if (!find_or_add_value( &others[V_VTXFMT], vfmt )) 1027 fprintf(stderr, " *** NEW VALUE"); 1028 1029 fprintf(stderr, "\n"); 1030 } 1031 1032 return 0; 1033 } 1034 #endif 1035 1036 static char *primname[0x10] = { 1037 "NONE", 1038 "POINTS", 1039 "LINES", 1040 "LINE_STRIP", 1041 "TRIANGLES", 1042 "TRIANGLE_FAN", 1043 "TRIANGLE_STRIP", 1044 "RECT_LIST", 1045 NULL, 1046 "3VRT_POINTS", 1047 "3VRT_LINES", 1048 "POINT_SPRITES", 1049 "LINE_LOOP", 1050 "QUADS", 1051 "QUAD_STRIP", 1052 "POLYGON", 1053 }; 1054 1055 static int print_prim_and_flags( int prim ) 1056 { 1057 int numverts; 1058 1059 if (NORMAL) 1060 fprintf(stderr, " %s(%x): %s%s%s%s%s%s\n", 1061 "prim flags", 1062 prim, 1063 ((prim & 0x30) == R200_VF_PRIM_WALK_IND) ? "IND," : "", 1064 ((prim & 0x30) == R200_VF_PRIM_WALK_LIST) ? "LIST," : "", 1065 ((prim & 0x30) == R200_VF_PRIM_WALK_RING) ? "RING," : "", 1066 (prim & R200_VF_COLOR_ORDER_RGBA) ? "RGBA," : "BGRA, ", 1067 (prim & R200_VF_INDEX_SZ_4) ? "INDX-32," : "", 1068 (prim & R200_VF_TCL_OUTPUT_VTX_ENABLE) ? "TCL_OUT_VTX," : ""); 1069 1070 numverts = prim>>16; 1071 1072 if (NORMAL) 1073 fprintf(stderr, " prim: %s numverts %d\n", primname[prim&0xf], numverts); 1074 1075 switch (prim & 0xf) { 1076 case R200_VF_PRIM_NONE: 1077 case R200_VF_PRIM_POINTS: 1078 if (numverts < 1) { 1079 fprintf(stderr, "Bad nr verts for line %d\n", numverts); 1080 return -1; 1081 } 1082 break; 1083 case R200_VF_PRIM_LINES: 1084 case R200_VF_PRIM_POINT_SPRITES: 1085 if ((numverts & 1) || numverts == 0) { 1086 fprintf(stderr, "Bad nr verts for line %d\n", numverts); 1087 return -1; 1088 } 1089 break; 1090 case R200_VF_PRIM_LINE_STRIP: 1091 case R200_VF_PRIM_LINE_LOOP: 1092 if (numverts < 2) { 1093 fprintf(stderr, "Bad nr verts for line_strip %d\n", numverts); 1094 return -1; 1095 } 1096 break; 1097 case R200_VF_PRIM_TRIANGLES: 1098 case R200_VF_PRIM_3VRT_POINTS: 1099 case R200_VF_PRIM_3VRT_LINES: 1100 case R200_VF_PRIM_RECT_LIST: 1101 if (numverts % 3 || numverts == 0) { 1102 fprintf(stderr, "Bad nr verts for tri %d\n", numverts); 1103 return -1; 1104 } 1105 break; 1106 case R200_VF_PRIM_TRIANGLE_FAN: 1107 case R200_VF_PRIM_TRIANGLE_STRIP: 1108 case R200_VF_PRIM_POLYGON: 1109 if (numverts < 3) { 1110 fprintf(stderr, "Bad nr verts for strip/fan %d\n", numverts); 1111 return -1; 1112 } 1113 break; 1114 case R200_VF_PRIM_QUADS: 1115 if (numverts % 4 || numverts == 0) { 1116 fprintf(stderr, "Bad nr verts for quad %d\n", numverts); 1117 return -1; 1118 } 1119 break; 1120 case R200_VF_PRIM_QUAD_STRIP: 1121 if (numverts % 2 || numverts < 4) { 1122 fprintf(stderr, "Bad nr verts for quadstrip %d\n", numverts); 1123 return -1; 1124 } 1125 break; 1126 default: 1127 fprintf(stderr, "Bad primitive\n"); 1128 return -1; 1129 } 1130 return 0; 1131 } 1132 1133 /* build in knowledge about each packet type 1134 */ 1135 static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf ) 1136 { 1137 int cmdsz; 1138 int *cmd = (int *)cmdbuf->buf; 1139 int *tmp; 1140 int i, stride, size, start; 1141 1142 cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); 1143 1144 if ((cmd[0] & RADEON_CP_PACKET_MASK) != RADEON_CP_PACKET3 || 1145 cmdsz * 4 > cmdbuf->bufsz || 1146 cmdsz > RADEON_CP_PACKET_MAX_DWORDS) { 1147 fprintf(stderr, "Bad packet\n"); 1148 return -EINVAL; 1149 } 1150 1151 switch( cmd[0] & ~RADEON_CP_PACKET_COUNT_MASK ) { 1152 case R200_CP_CMD_NOP: 1153 if (NORMAL) 1154 fprintf(stderr, "PACKET3_NOP, %d dwords\n", cmdsz); 1155 break; 1156 case R200_CP_CMD_NEXT_CHAR: 1157 if (NORMAL) 1158 fprintf(stderr, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz); 1159 break; 1160 case R200_CP_CMD_PLY_NEXTSCAN: 1161 if (NORMAL) 1162 fprintf(stderr, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz); 1163 break; 1164 case R200_CP_CMD_SET_SCISSORS: 1165 if (NORMAL) 1166 fprintf(stderr, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz); 1167 break; 1168 case R200_CP_CMD_LOAD_MICROCODE: 1169 if (NORMAL) 1170 fprintf(stderr, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz); 1171 break; 1172 case R200_CP_CMD_WAIT_FOR_IDLE: 1173 if (NORMAL) 1174 fprintf(stderr, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz); 1175 break; 1176 1177 case R200_CP_CMD_3D_DRAW_VBUF: 1178 if (NORMAL) 1179 fprintf(stderr, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz); 1180 /* print_vertex_format(cmd[1]); */ 1181 if (print_prim_and_flags(cmd[2])) 1182 return -EINVAL; 1183 break; 1184 1185 case R200_CP_CMD_3D_DRAW_IMMD: 1186 if (NORMAL) 1187 fprintf(stderr, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz); 1188 break; 1189 case R200_CP_CMD_3D_DRAW_INDX: { 1190 int neltdwords; 1191 if (NORMAL) 1192 fprintf(stderr, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz); 1193 /* print_vertex_format(cmd[1]); */ 1194 if (print_prim_and_flags(cmd[2])) 1195 return -EINVAL; 1196 neltdwords = cmd[2]>>16; 1197 neltdwords += neltdwords & 1; 1198 neltdwords /= 2; 1199 if (neltdwords + 3 != cmdsz) 1200 fprintf(stderr, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n", 1201 neltdwords, cmdsz); 1202 break; 1203 } 1204 case R200_CP_CMD_LOAD_PALETTE: 1205 if (NORMAL) 1206 fprintf(stderr, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz); 1207 break; 1208 case R200_CP_CMD_3D_LOAD_VBPNTR: 1209 if (NORMAL) { 1210 fprintf(stderr, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz); 1211 fprintf(stderr, " nr arrays: %d\n", cmd[1]); 1212 } 1213 1214 if (((cmd[1]/2)*3) + ((cmd[1]%2)*2) != cmdsz - 2) { 1215 fprintf(stderr, " ****** MISMATCH %d/%d *******\n", 1216 ((cmd[1]/2)*3) + ((cmd[1]%2)*2) + 2, cmdsz); 1217 return -EINVAL; 1218 } 1219 1220 if (NORMAL) { 1221 tmp = cmd+2; 1222 for (i = 0 ; i < cmd[1] ; i++) { 1223 if (i & 1) { 1224 stride = (tmp[0]>>24) & 0xff; 1225 size = (tmp[0]>>16) & 0xff; 1226 start = tmp[2]; 1227 tmp += 3; 1228 } 1229 else { 1230 stride = (tmp[0]>>8) & 0xff; 1231 size = (tmp[0]) & 0xff; 1232 start = tmp[1]; 1233 } 1234 fprintf(stderr, " array %d: start 0x%x vsize %d vstride %d\n", 1235 i, start, size, stride ); 1236 } 1237 } 1238 break; 1239 case R200_CP_CMD_PAINT: 1240 if (NORMAL) 1241 fprintf(stderr, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz); 1242 break; 1243 case R200_CP_CMD_BITBLT: 1244 if (NORMAL) 1245 fprintf(stderr, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz); 1246 break; 1247 case R200_CP_CMD_SMALLTEXT: 1248 if (NORMAL) 1249 fprintf(stderr, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz); 1250 break; 1251 case R200_CP_CMD_HOSTDATA_BLT: 1252 if (NORMAL) 1253 fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n", 1254 cmdsz); 1255 break; 1256 case R200_CP_CMD_POLYLINE: 1257 if (NORMAL) 1258 fprintf(stderr, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz); 1259 break; 1260 case R200_CP_CMD_POLYSCANLINES: 1261 if (NORMAL) 1262 fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n", 1263 cmdsz); 1264 break; 1265 case R200_CP_CMD_PAINT_MULTI: 1266 if (NORMAL) 1267 fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n", 1268 cmdsz); 1269 break; 1270 case R200_CP_CMD_BITBLT_MULTI: 1271 if (NORMAL) 1272 fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n", 1273 cmdsz); 1274 break; 1275 case R200_CP_CMD_TRANS_BITBLT: 1276 if (NORMAL) 1277 fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n", 1278 cmdsz); 1279 break; 1280 case R200_CP_CMD_3D_DRAW_VBUF_2: 1281 if (NORMAL) 1282 fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n", 1283 cmdsz); 1284 if (print_prim_and_flags(cmd[1])) 1285 return -EINVAL; 1286 break; 1287 case R200_CP_CMD_3D_DRAW_IMMD_2: 1288 if (NORMAL) 1289 fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n", 1290 cmdsz); 1291 if (print_prim_and_flags(cmd[1])) 1292 return -EINVAL; 1293 break; 1294 case R200_CP_CMD_3D_DRAW_INDX_2: 1295 if (NORMAL) 1296 fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n", 1297 cmdsz); 1298 if (print_prim_and_flags(cmd[1])) 1299 return -EINVAL; 1300 break; 1301 default: 1302 fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz); 1303 break; 1304 } 1305 1306 cmdbuf->buf += cmdsz * 4; 1307 cmdbuf->bufsz -= cmdsz * 4; 1308 return 0; 1309 } 1310 1311 1312 /* Check cliprects for bounds, then pass on to above: 1313 */ 1314 static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf ) 1315 { 1316 drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes; 1317 int i = 0; 1318 1319 if (VERBOSE && total_changed) { 1320 dump_state(); 1321 total_changed = 0; 1322 } 1323 1324 if (NORMAL) { 1325 do { 1326 if ( i < cmdbuf->nbox ) { 1327 fprintf(stderr, "Emit box %d/%d %d,%d %d,%d\n", 1328 i, cmdbuf->nbox, 1329 boxes[i].x1, boxes[i].y1, boxes[i].x2, boxes[i].y2); 1330 } 1331 } while ( ++i < cmdbuf->nbox ); 1332 } 1333 1334 if (cmdbuf->nbox == 1) 1335 cmdbuf->nbox = 0; 1336 1337 return radeon_emit_packet3( cmdbuf ); 1338 } 1339 1340 1341 int r200SanityCmdBuffer( r200ContextPtr rmesa, 1342 int nbox, 1343 drm_clip_rect_t *boxes ) 1344 { 1345 int idx; 1346 drm_radeon_cmd_buffer_t cmdbuf; 1347 drm_radeon_cmd_header_t header; 1348 static int inited = 0; 1349 1350 if (!inited) { 1351 init_regs(); 1352 inited = 1; 1353 } 1354 1355 1356 cmdbuf.buf = rmesa->store.cmd_buf; 1357 cmdbuf.bufsz = rmesa->store.cmd_used; 1358 cmdbuf.boxes = (drm_clip_rect_t *)boxes; 1359 cmdbuf.nbox = nbox; 1360 1361 while ( cmdbuf.bufsz >= sizeof(header) ) { 1362 1363 header.i = *(int *)cmdbuf.buf; 1364 cmdbuf.buf += sizeof(header); 1365 cmdbuf.bufsz -= sizeof(header); 1366 1367 switch (header.header.cmd_type) { 1368 case RADEON_CMD_PACKET: 1369 if (radeon_emit_packets( header, &cmdbuf )) { 1370 fprintf(stderr,"radeon_emit_packets failed\n"); 1371 return -EINVAL; 1372 } 1373 break; 1374 1375 case RADEON_CMD_SCALARS: 1376 if (radeon_emit_scalars( header, &cmdbuf )) { 1377 fprintf(stderr,"radeon_emit_scalars failed\n"); 1378 return -EINVAL; 1379 } 1380 break; 1381 1382 case RADEON_CMD_SCALARS2: 1383 if (radeon_emit_scalars2( header, &cmdbuf )) { 1384 fprintf(stderr,"radeon_emit_scalars failed\n"); 1385 return -EINVAL; 1386 } 1387 break; 1388 1389 case RADEON_CMD_VECTORS: 1390 if (radeon_emit_vectors( header, &cmdbuf )) { 1391 fprintf(stderr,"radeon_emit_vectors failed\n"); 1392 return -EINVAL; 1393 } 1394 break; 1395 1396 case RADEON_CMD_DMA_DISCARD: 1397 idx = header.dma.buf_idx; 1398 if (NORMAL) 1399 fprintf(stderr, "RADEON_CMD_DMA_DISCARD buf %d\n", idx); 1400 bufs++; 1401 break; 1402 1403 case RADEON_CMD_PACKET3: 1404 if (radeon_emit_packet3( &cmdbuf )) { 1405 fprintf(stderr,"radeon_emit_packet3 failed\n"); 1406 return -EINVAL; 1407 } 1408 break; 1409 1410 case RADEON_CMD_PACKET3_CLIP: 1411 if (radeon_emit_packet3_cliprect( &cmdbuf )) { 1412 fprintf(stderr,"radeon_emit_packet3_clip failed\n"); 1413 return -EINVAL; 1414 } 1415 break; 1416 1417 case RADEON_CMD_WAIT: 1418 break; 1419 1420 case RADEON_CMD_VECLINEAR: 1421 if (radeon_emit_veclinear( header, &cmdbuf )) { 1422 fprintf(stderr,"radeon_emit_veclinear failed\n"); 1423 return -EINVAL; 1424 } 1425 break; 1426 1427 default: 1428 fprintf(stderr,"bad cmd_type %d at %p\n", 1429 header.header.cmd_type, 1430 cmdbuf.buf - sizeof(header)); 1431 return -EINVAL; 1432 } 1433 } 1434 1435 if (0) 1436 { 1437 static int n = 0; 1438 n++; 1439 if (n == 10) { 1440 fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n", 1441 bufs, 1442 total, total_changed, 1443 ((float)total_changed/(float)total*100.0)); 1444 fprintf(stderr, "Total emitted per buf: %.2f\n", 1445 (float)total/(float)bufs); 1446 fprintf(stderr, "Real changes per buf: %.2f\n", 1447 (float)total_changed/(float)bufs); 1448 1449 bufs = n = total = total_changed = 0; 1450 } 1451 } 1452 1453 fprintf(stderr, "leaving %s\n\n\n", __FUNCTION__); 1454 1455 return 0; 1456 } 1457
