Lines Matching refs:Cycle
569 // need to erase the Cycle entries. They will be overwritten when we
609 // and instruction latencies. These cycle numbers assume that the CPU can issue
610 // an infinite number of instructions per cycle as long as their dependencies
687 unsigned Cycle;
693 LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(0), Op(0) {}
842 // Filter and process dependencies, computing the earliest issue cycle.
843 unsigned Cycle = 0;
857 Cycle = std::max(Cycle, DepCycle);
861 MICycles.Depth = Cycle;
864 DEBUG(dbgs() << Cycle << '\t' << *UseMI);
868 TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height);
869 DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << *UseMI);
899 unsigned DepHeight = I->Cycle;
918 if (LRU.Cycle <= Height && LRU.MI != MI) {
919 LRU.Cycle = Height;
1021 RegUnits[LI.Reg].Cycle = LI.Height;
1081 unsigned Cycle = 0;
1084 Cycle = HeightI->second;
1096 Cycle = updatePhysDepsUpwards(MI, Cycle, RegUnits,
1101 if (pushDepHeight(Deps[i], MI, Cycle, Heights, MTM.SchedModel, MTM.TII))
1105 MICycles.Height = Cycle;
1107 DEBUG(dbgs() << Cycle << '\t' << *MI);
1111 TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Depth);
1112 DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << *MI);
1128 TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle));
1130 << '@' << RI->Cycle);
1189 // Convert to cycle count.
1227 // Convert to cycle count.
