Home | History | Annotate | only in /external/llvm/lib/CodeGen
Up to higher level directory
NameDateSize
AggressiveAntiDepBreaker.cpp20-Jun-201433.9K
AggressiveAntiDepBreaker.h20-Jun-20147K
AllocationOrder.cpp20-Jun-20141.8K
AllocationOrder.h20-Jun-20142.6K
Analysis.cpp20-Jun-201423.3K
Android.mk20-Jun-20143.3K
AntiDepBreaker.h20-Jun-20142.6K
AsmPrinter/20-Jun-2014
BasicTargetTransformInfo.cpp20-Jun-201417.3K
BranchFolding.cpp20-Jun-201464K
BranchFolding.h20-Jun-20144.2K
CalcSpillWeights.cpp20-Jun-20146.7K
CallingConvLower.cpp20-Jun-20146.4K
CMakeLists.txt20-Jun-20142.6K
CodeGen.cpp20-Jun-20143.1K
CriticalAntiDepBreaker.cpp20-Jun-201425.4K
CriticalAntiDepBreaker.h20-Jun-20144.2K
DeadMachineInstructionElim.cpp20-Jun-20147K
DFAPacketizer.cpp20-Jun-20148.1K
DwarfEHPrepare.cpp20-Jun-20145.9K
EarlyIfConversion.cpp20-Jun-201428.3K
EdgeBundles.cpp20-Jun-20143.1K
ErlangGC.cpp20-Jun-20142.5K
ExecutionDepsFix.cpp20-Jun-201423.3K
ExpandISelPseudos.cpp20-Jun-20142.5K
ExpandPostRAPseudos.cpp20-Jun-20147.1K
GCMetadata.cpp20-Jun-20144.9K
GCMetadataPrinter.cpp20-Jun-2014824
GCStrategy.cpp20-Jun-201414.1K
IfConversion.cpp20-Jun-201457.1K
InlineSpiller.cpp20-Jun-201446.9K
InterferenceCache.cpp20-Jun-20147.5K
InterferenceCache.h20-Jun-20146.8K
IntrinsicLowering.cpp20-Jun-201421.1K
JITCodeEmitter.cpp20-Jun-2014440
LatencyPriorityQueue.cpp20-Jun-20145.5K
LexicalScopes.cpp20-Jun-201410.9K
LiveDebugVariables.cpp20-Jun-201434.1K
LiveDebugVariables.h20-Jun-20142.3K
LiveInterval.cpp20-Jun-201430.7K
LiveIntervalAnalysis.cpp20-Jun-201442K
LiveIntervalUnion.cpp20-Jun-20146.4K
LiveRangeCalc.cpp20-Jun-201413K
LiveRangeCalc.h20-Jun-20149.9K
LiveRangeEdit.cpp20-Jun-201413.6K
LiveRegMatrix.cpp20-Jun-20145.3K
LiveStackAnalysis.cpp20-Jun-20142.8K
LiveVariables.cpp20-Jun-201430.1K
LLVMBuild.txt20-Jun-2014803
LLVMTargetMachine.cpp20-Jun-201411.3K
LocalStackSlotAllocation.cpp20-Jun-201414.3K
MachineBasicBlock.cpp20-Jun-201441.9K
MachineBlockFrequencyInfo.cpp20-Jun-20142K
MachineBlockPlacement.cpp20-Jun-201448.2K
MachineBranchProbabilityInfo.cpp20-Jun-20144.2K
MachineCodeEmitter.cpp20-Jun-2014449
MachineCopyPropagation.cpp20-Jun-201411.1K
MachineCSE.cpp20-Jun-201422.7K
MachineDominators.cpp20-Jun-20141.7K
MachineFunction.cpp20-Jun-201432.8K
MachineFunctionAnalysis.cpp20-Jun-20141.8K
MachineFunctionPass.cpp20-Jun-20142K
MachineFunctionPrinterPass.cpp20-Jun-20142.1K
MachineInstr.cpp20-Jun-201464.2K
MachineInstrBundle.cpp20-Jun-201410.6K
MachineLICM.cpp20-Jun-201453.3K
MachineLoopInfo.cpp20-Jun-20142.8K
MachineModuleInfo.cpp20-Jun-201420.2K
MachineModuleInfoImpls.cpp20-Jun-20141.6K
MachinePassRegistry.cpp20-Jun-20141.7K
MachinePostDominators.cpp20-Jun-20141.7K
MachineRegisterInfo.cpp20-Jun-201414.4K
MachineScheduler.cpp20-Jun-201497K
MachineSink.cpp20-Jun-201425.1K
MachineSSAUpdater.cpp20-Jun-201413.2K
MachineTraceMetrics.cpp20-Jun-201448.5K
MachineVerifier.cpp20-Jun-201462.1K
Makefile20-Jun-2014719
OcamlGC.cpp20-Jun-2014999
OptimizePHIs.cpp20-Jun-20146.3K
Passes.cpp20-Jun-201428.9K
PeepholeOptimizer.cpp20-Jun-201419.7K
PHIElimination.cpp20-Jun-201425.6K
PHIEliminationUtils.cpp20-Jun-20142.3K
PHIEliminationUtils.h20-Jun-2014936
PostRASchedulerList.cpp20-Jun-201426.6K
ProcessImplicitDefs.cpp20-Jun-20145.5K
PrologEpilogInserter.cpp20-Jun-201435.6K
PrologEpilogInserter.h20-Jun-20146.2K
PseudoSourceValue.cpp20-Jun-20144K
README.txt20-Jun-20146.2K
RegAllocBase.cpp20-Jun-20145.3K
RegAllocBase.h20-Jun-20143.9K
RegAllocBasic.cpp20-Jun-201410.3K
RegAllocFast.cpp20-Jun-201440.6K
RegAllocGreedy.cpp20-Jun-201466.7K
RegAllocPBQP.cpp20-Jun-201421.2K
RegisterClassInfo.cpp20-Jun-20146.1K
RegisterCoalescer.cpp20-Jun-201484.4K
RegisterCoalescer.h20-Jun-20144.4K
RegisterPressure.cpp20-Jun-201429.6K
RegisterScavenging.cpp20-Jun-201414K
ScheduleDAG.cpp20-Jun-201419.8K
ScheduleDAGInstrs.cpp20-Jun-201449.9K
ScheduleDAGPrinter.cpp20-Jun-20143.2K
ScoreboardHazardRecognizer.cpp20-Jun-20147.9K
SelectionDAG/20-Jun-2014
ShadowStackGC.cpp20-Jun-201417.1K
ShrinkWrapping.cpp20-Jun-201439.3K
SjLjEHPrepare.cpp20-Jun-201420.1K
SlotIndexes.cpp20-Jun-20148.1K
Spiller.cpp20-Jun-20146.1K
Spiller.h20-Jun-20141.3K
SpillPlacement.cpp20-Jun-201412.7K
SpillPlacement.h20-Jun-20146.1K
SplitKit.cpp20-Jun-201450K
SplitKit.h20-Jun-201419.2K
StackColoring.cpp20-Jun-201428.6K
StackProtector.cpp20-Jun-201414.9K
StackSlotColoring.cpp20-Jun-201415.2K
StrongPHIElimination.cpp20-Jun-201431.9K
TailDuplication.cpp20-Jun-201434.5K
TargetFrameLoweringImpl.cpp20-Jun-20141.7K
TargetInstrInfo.cpp20-Jun-201426.1K
TargetLoweringBase.cpp20-Jun-201449.1K
TargetLoweringObjectFileImpl.cpp20-Jun-201429.8K
TargetOptionsImpl.cpp20-Jun-20142.2K
TargetRegisterInfo.cpp20-Jun-201410.5K
TargetSchedule.cpp20-Jun-201410.7K
TwoAddressInstructionPass.cpp20-Jun-201459K
UnreachableBlockElim.cpp20-Jun-20147.3K
VirtRegMap.cpp20-Jun-201412.4K

README.txt

      1 //===---------------------------------------------------------------------===//
      2 
      3 Common register allocation / spilling problem:
      4 
      5         mul lr, r4, lr
      6         str lr, [sp, #+52]
      7         ldr lr, [r1, #+32]
      8         sxth r3, r3
      9         ldr r4, [sp, #+52]
     10         mla r4, r3, lr, r4
     11 
     12 can be:
     13 
     14         mul lr, r4, lr
     15         mov r4, lr
     16         str lr, [sp, #+52]
     17         ldr lr, [r1, #+32]
     18         sxth r3, r3
     19         mla r4, r3, lr, r4
     20 
     21 and then "merge" mul and mov:
     22 
     23         mul r4, r4, lr
     24         str r4, [sp, #+52]
     25         ldr lr, [r1, #+32]
     26         sxth r3, r3
     27         mla r4, r3, lr, r4
     28 
     29 It also increase the likelihood the store may become dead.
     30 
     31 //===---------------------------------------------------------------------===//
     32 
     33 bb27 ...
     34         ...
     35         %reg1037 = ADDri %reg1039, 1
     36         %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
     37     Successors according to CFG: 0x8b03bf0 (#5)
     38 
     39 bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
     40     Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
     41         %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
     42 
     43 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
     44 operand of the PHI node in bb76 and its operand %reg1039 is the result of the
     45 PHI node. We should treat it as a two-address code and make sure the ADDri is
     46 scheduled after any node that reads %reg1039.
     47 
     48 //===---------------------------------------------------------------------===//
     49 
     50 Use local info (i.e. register scavenger) to assign it a free register to allow
     51 reuse:
     52         ldr r3, [sp, #+4]
     53         add r3, r3, #3
     54         ldr r2, [sp, #+8]
     55         add r2, r2, #2
     56         ldr r1, [sp, #+4]  <==
     57         add r1, r1, #1
     58         ldr r0, [sp, #+4]
     59         add r0, r0, #2
     60 
     61 //===---------------------------------------------------------------------===//
     62 
     63 LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
     64 effects:
     65 
     66 R1 = X + 4
     67 R2 = X + 7
     68 R3 = X + 15
     69 
     70 loop:
     71 load [i + R1]
     72 ...
     73 load [i + R2]
     74 ...
     75 load [i + R3]
     76 
     77 Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
     78 to implement proper re-materialization to handle this:
     79 
     80 R1 = X + 4
     81 R2 = X + 7
     82 R3 = X + 15
     83 
     84 loop:
     85 R1 = X + 4  @ re-materialized
     86 load [i + R1]
     87 ...
     88 R2 = X + 7 @ re-materialized
     89 load [i + R2]
     90 ...
     91 R3 = X + 15 @ re-materialized
     92 load [i + R3]
     93 
     94 Furthermore, with re-association, we can enable sharing:
     95 
     96 R1 = X + 4
     97 R2 = X + 7
     98 R3 = X + 15
     99 
    100 loop:
    101 T = i + X
    102 load [T + 4]
    103 ...
    104 load [T + 7]
    105 ...
    106 load [T + 15]
    107 //===---------------------------------------------------------------------===//
    108 
    109 It's not always a good idea to choose rematerialization over spilling. If all
    110 the load / store instructions would be folded then spilling is cheaper because
    111 it won't require new live intervals / registers. See 2003-05-31-LongShifts for
    112 an example.
    113 
    114 //===---------------------------------------------------------------------===//
    115 
    116 With a copying garbage collector, derived pointers must not be retained across
    117 collector safe points; the collector could move the objects and invalidate the
    118 derived pointer. This is bad enough in the first place, but safe points can
    119 crop up unpredictably. Consider:
    120 
    121         %array = load { i32, [0 x %obj] }** %array_addr
    122         %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
    123         %old = load %obj** %nth_el
    124         %z = div i64 %x, %y
    125         store %obj* %new, %obj** %nth_el
    126 
    127 If the i64 division is lowered to a libcall, then a safe point will (must)
    128 appear for the call site. If a collection occurs, %array and %nth_el no longer
    129 point into the correct object.
    130 
    131 The fix for this is to copy address calculations so that dependent pointers
    132 are never live across safe point boundaries. But the loads cannot be copied
    133 like this if there was an intervening store, so may be hard to get right.
    134 
    135 Only a concurrent mutator can trigger a collection at the libcall safe point.
    136 So single-threaded programs do not have this requirement, even with a copying
    137 collector. Still, LLVM optimizations would probably undo a front-end's careful
    138 work.
    139 
    140 //===---------------------------------------------------------------------===//
    141 
    142 The ocaml frametable structure supports liveness information. It would be good
    143 to support it.
    144 
    145 //===---------------------------------------------------------------------===//
    146 
    147 The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
    148 revisited. The check is there to work around a misuse of directives in inline
    149 assembly.
    150 
    151 //===---------------------------------------------------------------------===//
    152 
    153 It would be good to detect collector/target compatibility instead of silently
    154 doing the wrong thing.
    155 
    156 //===---------------------------------------------------------------------===//
    157 
    158 It would be really nice to be able to write patterns in .td files for copies,
    159 which would eliminate a bunch of explicit predicates on them (e.g. no side 
    160 effects).  Once this is in place, it would be even better to have tblgen 
    161 synthesize the various copy insertion/inspection methods in TargetInstrInfo.
    162 
    163 //===---------------------------------------------------------------------===//
    164 
    165 Stack coloring improvements:
    166 
    167 1. Do proper LiveStackAnalysis on all stack objects including those which are
    168    not spill slots.
    169 2. Reorder objects to fill in gaps between objects.
    170    e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4
    171 
    172 //===---------------------------------------------------------------------===//
    173 
    174 The scheduler should be able to sort nearby instructions by their address. For
    175 example, in an expanded memset sequence it's not uncommon to see code like this:
    176 
    177   movl $0, 4(%rdi)
    178   movl $0, 8(%rdi)
    179   movl $0, 12(%rdi)
    180   movl $0, 0(%rdi)
    181 
    182 Each of the stores is independent, and the scheduler is currently making an
    183 arbitrary decision about the order.
    184 
    185 //===---------------------------------------------------------------------===//
    186 
    187 Another opportunitiy in this code is that the $0 could be moved to a register:
    188 
    189   movl $0, 4(%rdi)
    190   movl $0, 8(%rdi)
    191   movl $0, 12(%rdi)
    192   movl $0, 0(%rdi)
    193 
    194 This would save substantial code size, especially for longer sequences like
    195 this. It would be easy to have a rule telling isel to avoid matching MOV32mi
    196 if the immediate has more than some fixed number of uses. It's more involved
    197 to teach the register allocator how to do late folding to recover from
    198 excessive register pressure.
    199 
    200