Lines Matching refs:PredSU
365 SUnit *PredSU = PredEdge->getSUnit();
368 if (PredSU->NumSuccsLeft == 0) {
370 PredSU->dump(this);
375 --PredSU->NumSuccsLeft;
380 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
385 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
386 PredSU->isAvailable = true;
388 unsigned Height = PredSU->getHeight();
392 if (isReady(PredSU)) {
393 AvailableQueue->push(PredSU);
397 else if (!PredSU->isPending) {
398 PredSU->isPending = true;
399 PendingQueue.push_back(PredSU);
791 SUnit *PredSU = PredEdge->getSUnit();
792 if (PredSU->isAvailable) {
793 PredSU->isAvailable = false;
794 if (!PredSU->isPending)
795 AvailableQueue->remove(PredSU);
798 assert(PredSU->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
799 ++PredSU->NumSuccsLeft;
1850 SUnit *PredSU = I->getSUnit();
1851 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
1953 SUnit *PredSU = I->getSUnit();
1956 if (PredSU->NumRegDefsLeft == 0) {
1959 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2003 SUnit *PredSU = I->getSUnit();
2006 if (PredSU->NumRegDefsLeft == 0) {
2007 if (PredSU->getNode()->isMachineOpcode())
2011 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2047 SUnit *PredSU = I->getSUnit();
2050 if (PredSU->NumRegDefsLeft == 0) {
2065 // defs in PredSU. The can't be determined here, but we've already
2066 // compensated by reducing NumRegDefsLeft in PredSU during
2068 --PredSU->NumRegDefsLeft;
2069 unsigned SkipRegDefs = PredSU->NumRegDefsLeft;
2070 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2129 SUnit *PredSU = I->getSUnit();
2132 if (PredSU->NumSuccsLeft != PredSU->Succs.size())
2134 const SDNode *PN = PredSU->getNode();
2228 const SUnit *PredSU = I->getSUnit();
2229 if (PredSU->getNode() &&
2230 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
2232 cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
2302 SUnit *PredSU = I->getSUnit();
2303 if (PredSU->isVRegCycle) {
2304 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
2835 SUnit *PredSU = 0;
2839 PredSU = II->getSUnit();
2842 assert(PredSU);
2846 if (PredSU->hasPhysRegDefs)
2848 // Short-circuit the case where SU is PredSU's only data successor.
2849 if (PredSU->NumSuccs == 1)
2859 // Perform checks on the successors of PredSU.
2860 for (SUnit::const_succ_iterator II = PredSU->Succs.begin(),
2861 EE = PredSU->Succs.end(); II != EE; ++II) {
2864 // If PredSU has another successor with no data successors, for
2880 << " next to PredSU #" << PredSU->NodeNum
2882 for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {
2883 SDep Edge = PredSU->Succs[i];
2887 Edge.setSUnit(PredSU);
