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Lines Matching refs:ItinData

574 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
577 if (!ItinData || ItinData->isEmpty())
585 return ItinData->getOperandCycle(DefClass, DefIdx);
587 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
590 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
592 if (!ItinData || ItinData->isEmpty())
598 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
606 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
608 if (!ItinData || ItinData->isEmpty())
612 int UOps = ItinData->Itineraries[Class].NumMicroOps;
634 getInstrLatency(const InstrItineraryData *ItinData,
639 if (!ItinData)
642 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
645 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
648 if (!ItinData || ItinData->isEmpty())
652 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
659 getOperandLatency(const InstrItineraryData *ItinData,
664 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
670 const InstrItineraryData *ItinData,
674 if (!ItinData)
675 return getInstrLatency(ItinData, DefMI);
677 if(ItinData->isEmpty())
678 return defaultDefLatency(ItinData->SchedModel, DefMI);
696 computeOperandLatency(const InstrItineraryData *ItinData,
700 int DefLatency = computeDefOperandLatency(ItinData, DefMI);
704 assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
708 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
711 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
717 unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
721 defaultDefLatency(ItinData->SchedModel, DefMI));