Lines Matching refs:Encoded
234 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
239 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
255 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
259 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
260 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
261 return Encoded;
273 /// getSORegOpValue - Return an encoded so_reg shifted register value.
349 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
368 encoded NEON load/store
381 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
394 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
405 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
425 // Q registers are encoded as 2x their register number.
463 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
786 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
798 // FIXME: The immediate operand should have already been encoded like this
810 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
818 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
850 // FIXME: The immediate operand should have already been encoded like this
857 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
963 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1155 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1262 // Encoded as [Rn, Rm, imm].
1521 // Pseudo instructions don't get encoded.
