| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 475 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
495 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
500 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
569 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
574 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
577 DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
593 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
606 // Rn_wb, Rt, Rt2, Rn, Imm
607 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
616 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)
[all...] |
| /art/runtime/ |
| disassembler_arm.cc | 230 ArmRegister rn(instruction, 16);
231 if (rn.r == 0xf) {
237 args << "[" << rn << ", #" << offset << "]";
239 args << "[" << rn << ", #" << offset << "]!";
241 args << "[" << rn << "], #" << offset;
245 if (rn.r == 9) {
309 // |111|01|00|op|0|WL| Rn | |
318 ArmRegister Rn(instr, 16);
323 args << Rn << (W == 0 ? "" : "!") << ", ";
325 if (Rn.r != 13)
[all...] |
| /external/chromium_org/v8/src/arm/ |
| disasm-arm.cc | 114 void FormatNeonMemory(int Rn, int align, int Rm);
327 if (format[1] == 'n') { // 'rn: Rn register
440 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) {
442 "[r%d", Rn);
739 // Rn field to encode it.
740 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
744 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
745 // Rn field to encode the Rd register and the Rd field to encode
746 // the Rn register
[all...] |
| simulator-arm.cc | 1543 int rn = instr->RnValue(); local
2020 int rn = instr->RnValue(); local
2097 int rn = instr->RnValue(); local
2278 int rn = instr->RnValue(); local
2501 int rn = instr->RnValue(); local
2565 int rn = instr->RnValue(); local
3351 int rn = instr->RnValue(); local
3388 int rn = instr->RnValue(); local
3408 int rn = instr->RnValue(); local
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 735 // [Rn, Rm]
737 // {2-0} = Rn
740 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
742 return (Rm << 3) | Rn;
757 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
837 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/qemu/ |
| arm-dis.c | 1742 int rn = (given >> 16) & 0xf; local
2071 const char *rn = arm_regnames [(given >> 16) & 0xf]; local
2284 int rn = ((given >> 16) & 0xf); local
2314 int rn = ((given >> 16) & 0xf); local
2389 int rn = ((given >> 16) & 0xf); local
[all...] |
| trace.c | 896 int Rn = (insn >> 12) & 15;
899 result += _interlock_use(Rn);
901 if (Rn != 0) /* UNDEFINED */
934 int Rn = (insn >> 16) & 15;
936 result += _interlock_use(Rn) + _interlock_use(Rm);
943 int Rn = (insn >> 16) & 15;
945 result += _interlock_use(Rn);
957 int Rn = (insn >> 16) & 15;
959 result += _interlock_use(Rn) + _interlock_use(Rm);
970 int Rn = (insn >> 16) & 15
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
