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      1 //===- AArch64FrameLowering.cpp - AArch64 Frame Information ---------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the AArch64 implementation of TargetFrameLowering class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "AArch64.h"
     15 #include "AArch64FrameLowering.h"
     16 #include "AArch64MachineFunctionInfo.h"
     17 #include "AArch64InstrInfo.h"
     18 #include "llvm/CodeGen/MachineFrameInfo.h"
     19 #include "llvm/CodeGen/MachineFunction.h"
     20 #include "llvm/CodeGen/MachineInstrBuilder.h"
     21 #include "llvm/CodeGen/MachineMemOperand.h"
     22 #include "llvm/CodeGen/MachineModuleInfo.h"
     23 #include "llvm/CodeGen/MachineRegisterInfo.h"
     24 #include "llvm/CodeGen/RegisterScavenging.h"
     25 #include "llvm/IR/Function.h"
     26 #include "llvm/MC/MachineLocation.h"
     27 #include "llvm/Support/Debug.h"
     28 #include "llvm/Support/ErrorHandling.h"
     29 
     30 using namespace llvm;
     31 
     32 void AArch64FrameLowering::splitSPAdjustments(uint64_t Total,
     33                                               uint64_t &Initial,
     34                                               uint64_t &Residual) const {
     35   // 0x1f0 here is a pessimistic (i.e. realistic) boundary: x-register LDP
     36   // instructions have a 7-bit signed immediate scaled by 8, giving a reach of
     37   // 0x1f8, but stack adjustment should always be a multiple of 16.
     38   if (Total <= 0x1f0) {
     39     Initial = Total;
     40     Residual = 0;
     41   } else {
     42     Initial = 0x1f0;
     43     Residual = Total - Initial;
     44   }
     45 }
     46 
     47 void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
     48   AArch64MachineFunctionInfo *FuncInfo =
     49     MF.getInfo<AArch64MachineFunctionInfo>();
     50   MachineBasicBlock &MBB = MF.front();
     51   MachineBasicBlock::iterator MBBI = MBB.begin();
     52   MachineFrameInfo *MFI = MF.getFrameInfo();
     53   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
     54   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
     55 
     56   MachineModuleInfo &MMI = MF.getMMI();
     57   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
     58   bool NeedsFrameMoves = MMI.hasDebugInfo()
     59     || MF.getFunction()->needsUnwindTableEntry();
     60 
     61   uint64_t NumInitialBytes, NumResidualBytes;
     62 
     63   // Currently we expect the stack to be laid out by
     64   //     sub sp, sp, #initial
     65   //     stp x29, x30, [sp, #offset]
     66   //     ...
     67   //     str xxx, [sp, #offset]
     68   //     sub sp, sp, #rest (possibly via extra instructions).
     69   if (MFI->getCalleeSavedInfo().size()) {
     70     // If there are callee-saved registers, we want to store them efficiently as
     71     // a block, and virtual base assignment happens too early to do it for us so
     72     // we adjust the stack in two phases: first just for callee-saved fiddling,
     73     // then to allocate the rest of the frame.
     74     splitSPAdjustments(MFI->getStackSize(), NumInitialBytes, NumResidualBytes);
     75   } else {
     76     // If there aren't any callee-saved registers, two-phase adjustment is
     77     // inefficient. It's more efficient to adjust with NumInitialBytes too
     78     // because when we're in a "callee pops argument space" situation, that pop
     79     // must be tacked onto Initial for correctness.
     80     NumInitialBytes = MFI->getStackSize();
     81     NumResidualBytes = 0;
     82   }
     83 
     84   // Tell everyone else how much adjustment we're expecting them to use. In
     85   // particular if an adjustment is required for a tail call the epilogue could
     86   // have a different view of things.
     87   FuncInfo->setInitialStackAdjust(NumInitialBytes);
     88 
     89   emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes,
     90                MachineInstr::FrameSetup);
     91 
     92   if (NeedsFrameMoves && NumInitialBytes) {
     93     // We emit this update even if the CFA is set from a frame pointer later so
     94     // that the CFA is valid in the interim.
     95     MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
     96     BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
     97       .addSym(SPLabel);
     98 
     99     MachineLocation Dst(MachineLocation::VirtualFP);
    100     unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
    101     MMI.addFrameInst(
    102         MCCFIInstruction::createDefCfa(SPLabel, Reg, -NumInitialBytes));
    103   }
    104 
    105   // Otherwise we need to set the frame pointer and/or add a second stack
    106   // adjustment.
    107 
    108   bool FPNeedsSetting = hasFP(MF);
    109   for (; MBBI != MBB.end(); ++MBBI) {
    110     // Note that this search makes strong assumptions about the operation used
    111     // to store the frame-pointer: it must be "STP x29, x30, ...". This could
    112     // change in future, but until then there's no point in implementing
    113     // untestable more generic cases.
    114     if (FPNeedsSetting && MBBI->getOpcode() == AArch64::LSPair64_STR
    115                        && MBBI->getOperand(0).getReg() == AArch64::X29) {
    116       int64_t X29FrameIdx = MBBI->getOperand(2).getIndex();
    117       FuncInfo->setFramePointerOffset(MFI->getObjectOffset(X29FrameIdx));
    118 
    119       ++MBBI;
    120       emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP,
    121                     AArch64::X29,
    122                     NumInitialBytes + MFI->getObjectOffset(X29FrameIdx),
    123                     MachineInstr::FrameSetup);
    124 
    125       // The offset adjustment used when emitting debugging locations relative
    126       // to whatever frame base is set. AArch64 uses the default frame base (FP
    127       // or SP) and this adjusts the calculations to be correct.
    128       MFI->setOffsetAdjustment(- MFI->getObjectOffset(X29FrameIdx)
    129                                - MFI->getStackSize());
    130 
    131       if (NeedsFrameMoves) {
    132         MCSymbol *FPLabel = MMI.getContext().CreateTempSymbol();
    133         BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
    134           .addSym(FPLabel);
    135         unsigned Reg = MRI->getDwarfRegNum(AArch64::X29, true);
    136         unsigned Offset = MFI->getObjectOffset(X29FrameIdx);
    137         MMI.addFrameInst(MCCFIInstruction::createDefCfa(FPLabel, Reg, Offset));
    138       }
    139 
    140       FPNeedsSetting = false;
    141     }
    142 
    143     if (!MBBI->getFlag(MachineInstr::FrameSetup))
    144       break;
    145   }
    146 
    147   assert(!FPNeedsSetting && "Frame pointer couldn't be set");
    148 
    149   emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumResidualBytes,
    150                MachineInstr::FrameSetup);
    151 
    152   // Now we emit the rest of the frame setup information, if necessary: we've
    153   // already noted the FP and initial SP moves so we're left with the prologue's
    154   // final SP update and callee-saved register locations.
    155   if (!NeedsFrameMoves)
    156     return;
    157 
    158   // Reuse the label if appropriate, so create it in this outer scope.
    159   MCSymbol *CSLabel = 0;
    160 
    161   // The rest of the stack adjustment
    162   if (!hasFP(MF) && NumResidualBytes) {
    163     CSLabel = MMI.getContext().CreateTempSymbol();
    164     BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
    165       .addSym(CSLabel);
    166 
    167     MachineLocation Dst(MachineLocation::VirtualFP);
    168     unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
    169     unsigned Offset = NumResidualBytes + NumInitialBytes;
    170     MMI.addFrameInst(MCCFIInstruction::createDefCfa(CSLabel, Reg, -Offset));
    171   }
    172 
    173   // And any callee-saved registers (it's fine to leave them to the end here,
    174   // because the old values are still valid at this point.
    175   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
    176   if (CSI.size()) {
    177     if (!CSLabel) {
    178       CSLabel = MMI.getContext().CreateTempSymbol();
    179       BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
    180         .addSym(CSLabel);
    181     }
    182 
    183     for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
    184            E = CSI.end(); I != E; ++I) {
    185       unsigned Offset = MFI->getObjectOffset(I->getFrameIdx());
    186       unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
    187       MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, Reg, Offset));
    188     }
    189   }
    190 }
    191 
    192 void
    193 AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
    194                                    MachineBasicBlock &MBB) const {
    195   AArch64MachineFunctionInfo *FuncInfo =
    196     MF.getInfo<AArch64MachineFunctionInfo>();
    197 
    198   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
    199   DebugLoc DL = MBBI->getDebugLoc();
    200   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    201   MachineFrameInfo &MFI = *MF.getFrameInfo();
    202   unsigned RetOpcode = MBBI->getOpcode();
    203 
    204   // Initial and residual are named for consitency with the prologue. Note that
    205   // in the epilogue, the residual adjustment is executed first.
    206   uint64_t NumInitialBytes = FuncInfo->getInitialStackAdjust();
    207   uint64_t NumResidualBytes = MFI.getStackSize() - NumInitialBytes;
    208   uint64_t ArgumentPopSize = 0;
    209   if (RetOpcode == AArch64::TC_RETURNdi ||
    210       RetOpcode == AArch64::TC_RETURNxi) {
    211     MachineOperand &JumpTarget = MBBI->getOperand(0);
    212     MachineOperand &StackAdjust = MBBI->getOperand(1);
    213 
    214     MachineInstrBuilder MIB;
    215     if (RetOpcode == AArch64::TC_RETURNdi) {
    216       MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
    217       if (JumpTarget.isGlobal()) {
    218         MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
    219                              JumpTarget.getTargetFlags());
    220       } else {
    221         assert(JumpTarget.isSymbol() && "unexpected tail call destination");
    222         MIB.addExternalSymbol(JumpTarget.getSymbolName(),
    223                               JumpTarget.getTargetFlags());
    224       }
    225     } else {
    226       assert(RetOpcode == AArch64::TC_RETURNxi && JumpTarget.isReg()
    227              && "Unexpected tail call");
    228 
    229       MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
    230       MIB.addReg(JumpTarget.getReg(), RegState::Kill);
    231     }
    232 
    233     // Add the extra operands onto the new tail call instruction even though
    234     // they're not used directly (so that liveness is tracked properly etc).
    235     for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
    236         MIB->addOperand(MBBI->getOperand(i));
    237 
    238 
    239     // Delete the pseudo instruction TC_RETURN.
    240     MachineInstr *NewMI = prior(MBBI);
    241     MBB.erase(MBBI);
    242     MBBI = NewMI;
    243 
    244     // For a tail-call in a callee-pops-arguments environment, some or all of
    245     // the stack may actually be in use for the call's arguments, this is
    246     // calculated during LowerCall and consumed here...
    247     ArgumentPopSize = StackAdjust.getImm();
    248   } else {
    249     // ... otherwise the amount to pop is *all* of the argument space,
    250     // conveniently stored in the MachineFunctionInfo by
    251     // LowerFormalArguments. This will, of course, be zero for the C calling
    252     // convention.
    253     ArgumentPopSize = FuncInfo->getArgumentStackToRestore();
    254   }
    255 
    256   assert(NumInitialBytes % 16 == 0 && NumResidualBytes % 16 == 0
    257          && "refusing to adjust stack by misaligned amt");
    258 
    259   // We may need to address callee-saved registers differently, so find out the
    260   // bound on the frame indices.
    261   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
    262   int MinCSFI = 0;
    263   int MaxCSFI = -1;
    264 
    265   if (CSI.size()) {
    266     MinCSFI = CSI[0].getFrameIdx();
    267     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
    268   }
    269 
    270   // The "residual" stack update comes first from this direction and guarantees
    271   // that SP is NumInitialBytes below its value on function entry, either by a
    272   // direct update or restoring it from the frame pointer.
    273   if (NumInitialBytes + ArgumentPopSize != 0) {
    274     emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16,
    275                  NumInitialBytes + ArgumentPopSize);
    276     --MBBI;
    277   }
    278 
    279 
    280   // MBBI now points to the instruction just past the last callee-saved
    281   // restoration (either RET/B if NumInitialBytes == 0, or the "ADD sp, sp"
    282   // otherwise).
    283 
    284   // Now we need to find out where to put the bulk of the stack adjustment
    285   MachineBasicBlock::iterator FirstEpilogue = MBBI;
    286   while (MBBI != MBB.begin()) {
    287     --MBBI;
    288 
    289     unsigned FrameOp;
    290     for (FrameOp = 0; FrameOp < MBBI->getNumOperands(); ++FrameOp) {
    291       if (MBBI->getOperand(FrameOp).isFI())
    292         break;
    293     }
    294 
    295     // If this instruction doesn't have a frame index we've reached the end of
    296     // the callee-save restoration.
    297     if (FrameOp == MBBI->getNumOperands())
    298       break;
    299 
    300     // Likewise if it *is* a local reference, but not to a callee-saved object.
    301     int FrameIdx = MBBI->getOperand(FrameOp).getIndex();
    302     if (FrameIdx < MinCSFI || FrameIdx > MaxCSFI)
    303       break;
    304 
    305     FirstEpilogue = MBBI;
    306   }
    307 
    308   if (MF.getFrameInfo()->hasVarSizedObjects()) {
    309     int64_t StaticFrameBase;
    310     StaticFrameBase = -(NumInitialBytes + FuncInfo->getFramePointerOffset());
    311     emitRegUpdate(MBB, FirstEpilogue, DL, TII,
    312                   AArch64::XSP, AArch64::X29, AArch64::NoRegister,
    313                   StaticFrameBase);
    314   } else {
    315     emitSPUpdate(MBB, FirstEpilogue, DL,TII, AArch64::X16, NumResidualBytes);
    316   }
    317 }
    318 
    319 int64_t
    320 AArch64FrameLowering::resolveFrameIndexReference(MachineFunction &MF,
    321                                                  int FrameIndex,
    322                                                  unsigned &FrameReg,
    323                                                  int SPAdj,
    324                                                  bool IsCalleeSaveOp) const {
    325   AArch64MachineFunctionInfo *FuncInfo =
    326     MF.getInfo<AArch64MachineFunctionInfo>();
    327   MachineFrameInfo *MFI = MF.getFrameInfo();
    328 
    329   int64_t TopOfFrameOffset = MFI->getObjectOffset(FrameIndex);
    330 
    331   assert(!(IsCalleeSaveOp && FuncInfo->getInitialStackAdjust() == 0)
    332          && "callee-saved register in unexpected place");
    333 
    334   // If the frame for this function is particularly large, we adjust the stack
    335   // in two phases which means the callee-save related operations see a
    336   // different (intermediate) stack size.
    337   int64_t FrameRegPos;
    338   if (IsCalleeSaveOp) {
    339     FrameReg = AArch64::XSP;
    340     FrameRegPos = -static_cast<int64_t>(FuncInfo->getInitialStackAdjust());
    341   } else if (useFPForAddressing(MF)) {
    342     // Have to use the frame pointer since we have no idea where SP is.
    343     FrameReg = AArch64::X29;
    344     FrameRegPos = FuncInfo->getFramePointerOffset();
    345   } else {
    346     FrameReg = AArch64::XSP;
    347     FrameRegPos = -static_cast<int64_t>(MFI->getStackSize()) + SPAdj;
    348   }
    349 
    350   return TopOfFrameOffset - FrameRegPos;
    351 }
    352 
    353 void
    354 AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
    355                                                        RegScavenger *RS) const {
    356   const AArch64RegisterInfo *RegInfo =
    357     static_cast<const AArch64RegisterInfo *>(MF.getTarget().getRegisterInfo());
    358   MachineFrameInfo *MFI = MF.getFrameInfo();
    359   const AArch64InstrInfo &TII =
    360     *static_cast<const AArch64InstrInfo *>(MF.getTarget().getInstrInfo());
    361 
    362   if (hasFP(MF)) {
    363     MF.getRegInfo().setPhysRegUsed(AArch64::X29);
    364     MF.getRegInfo().setPhysRegUsed(AArch64::X30);
    365   }
    366 
    367   // If addressing of local variables is going to be more complicated than
    368   // shoving a base register and an offset into the instruction then we may well
    369   // need to scavenge registers. We should either specifically add an
    370   // callee-save register for this purpose or allocate an extra spill slot.
    371   bool BigStack =
    372     MFI->estimateStackSize(MF) >= TII.estimateRSStackLimit(MF)
    373     || MFI->hasVarSizedObjects() // Access will be from X29: messes things up
    374     || (MFI->adjustsStack() && !hasReservedCallFrame(MF));
    375 
    376   if (!BigStack)
    377     return;
    378 
    379   // We certainly need some slack space for the scavenger, preferably an extra
    380   // register.
    381   const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
    382   uint16_t ExtraReg = AArch64::NoRegister;
    383 
    384   for (unsigned i = 0; CSRegs[i]; ++i) {
    385     if (AArch64::GPR64RegClass.contains(CSRegs[i]) &&
    386         !MF.getRegInfo().isPhysRegUsed(CSRegs[i])) {
    387       ExtraReg = CSRegs[i];
    388       break;
    389     }
    390   }
    391 
    392   if (ExtraReg != 0) {
    393     MF.getRegInfo().setPhysRegUsed(ExtraReg);
    394   } else {
    395     assert(RS && "Expect register scavenger to be available");
    396 
    397     // Create a stack slot for scavenging purposes. PrologEpilogInserter
    398     // helpfully places it near either SP or FP for us to avoid
    399     // infinitely-regression during scavenging.
    400     const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
    401     RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
    402                                                        RC->getAlignment(),
    403                                                        false));
    404   }
    405 }
    406 
    407 bool AArch64FrameLowering::determinePrologueDeath(MachineBasicBlock &MBB,
    408                                                   unsigned Reg) const {
    409   // If @llvm.returnaddress is called then it will refer to X30 by some means;
    410   // the prologue store does not kill the register.
    411   if (Reg == AArch64::X30) {
    412     if (MBB.getParent()->getFrameInfo()->isReturnAddressTaken()
    413         && MBB.getParent()->getRegInfo().isLiveIn(Reg))
    414     return false;
    415   }
    416 
    417   // In all other cases, physical registers are dead after they've been saved
    418   // but live at the beginning of the prologue block.
    419   MBB.addLiveIn(Reg);
    420   return true;
    421 }
    422 
    423 void
    424 AArch64FrameLowering::emitFrameMemOps(bool isPrologue, MachineBasicBlock &MBB,
    425                                       MachineBasicBlock::iterator MBBI,
    426                                       const std::vector<CalleeSavedInfo> &CSI,
    427                                       const TargetRegisterInfo *TRI,
    428                                       const LoadStoreMethod PossClasses[],
    429                                       unsigned NumClasses) const {
    430   DebugLoc DL = MBB.findDebugLoc(MBBI);
    431   MachineFunction &MF = *MBB.getParent();
    432   MachineFrameInfo &MFI = *MF.getFrameInfo();
    433   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    434 
    435   // A certain amount of implicit contract is present here. The actual stack
    436   // offsets haven't been allocated officially yet, so for strictly correct code
    437   // we rely on the fact that the elements of CSI are allocated in order
    438   // starting at SP, purely as dictated by size and alignment. In practice since
    439   // this function handles the only accesses to those slots it's not quite so
    440   // important.
    441   //
    442   // We have also ordered the Callee-saved register list in AArch64CallingConv
    443   // so that the above scheme puts registers in order: in particular we want
    444   // &X30 to be &X29+8 for an ABI-correct frame record (PCS 5.2.2)
    445   for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
    446     unsigned Reg = CSI[i].getReg();
    447 
    448     // First we need to find out which register class the register belongs to so
    449     // that we can use the correct load/store instrucitons.
    450     unsigned ClassIdx;
    451     for (ClassIdx = 0; ClassIdx < NumClasses; ++ClassIdx) {
    452       if (PossClasses[ClassIdx].RegClass->contains(Reg))
    453         break;
    454     }
    455     assert(ClassIdx != NumClasses
    456            && "Asked to store register in unexpected class");
    457     const TargetRegisterClass &TheClass = *PossClasses[ClassIdx].RegClass;
    458 
    459     // Now we need to decide whether it's possible to emit a paired instruction:
    460     // for this we want the next register to be in the same class.
    461     MachineInstrBuilder NewMI;
    462     bool Pair = false;
    463     if (i + 1 < CSI.size() && TheClass.contains(CSI[i+1].getReg())) {
    464       Pair = true;
    465       unsigned StLow = 0, StHigh = 0;
    466       if (isPrologue) {
    467         // Most of these registers will be live-in to the MBB and killed by our
    468         // store, though there are exceptions (see determinePrologueDeath).
    469         StLow = getKillRegState(determinePrologueDeath(MBB, CSI[i+1].getReg()));
    470         StHigh = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
    471       } else {
    472         StLow = RegState::Define;
    473         StHigh = RegState::Define;
    474       }
    475 
    476       NewMI = BuildMI(MBB, MBBI, DL, TII.get(PossClasses[ClassIdx].PairOpcode))
    477                 .addReg(CSI[i+1].getReg(), StLow)
    478                 .addReg(CSI[i].getReg(), StHigh);
    479 
    480       // If it's a paired op, we've consumed two registers
    481       ++i;
    482     } else {
    483       unsigned State;
    484       if (isPrologue) {
    485         State = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
    486       } else {
    487         State = RegState::Define;
    488       }
    489 
    490       NewMI = BuildMI(MBB, MBBI, DL,
    491                       TII.get(PossClasses[ClassIdx].SingleOpcode))
    492                 .addReg(CSI[i].getReg(), State);
    493     }
    494 
    495     // Note that the FrameIdx refers to the second register in a pair: it will
    496     // be allocated the smaller numeric address and so is the one an LDP/STP
    497     // address must use.
    498     int FrameIdx = CSI[i].getFrameIdx();
    499     MachineMemOperand::MemOperandFlags Flags;
    500     Flags = isPrologue ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;
    501     MachineMemOperand *MMO =
    502       MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
    503                              Flags,
    504                              Pair ? TheClass.getSize() * 2 : TheClass.getSize(),
    505                              MFI.getObjectAlignment(FrameIdx));
    506 
    507     NewMI.addFrameIndex(FrameIdx)
    508       .addImm(0)                  // address-register offset
    509       .addMemOperand(MMO);
    510 
    511     if (isPrologue)
    512       NewMI.setMIFlags(MachineInstr::FrameSetup);
    513 
    514     // For aesthetic reasons, during an epilogue we want to emit complementary
    515     // operations to the prologue, but in the opposite order. So we still
    516     // iterate through the CalleeSavedInfo list in order, but we put the
    517     // instructions successively earlier in the MBB.
    518     if (!isPrologue)
    519       --MBBI;
    520   }
    521 }
    522 
    523 bool
    524 AArch64FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
    525                                         MachineBasicBlock::iterator MBBI,
    526                                         const std::vector<CalleeSavedInfo> &CSI,
    527                                         const TargetRegisterInfo *TRI) const {
    528   if (CSI.empty())
    529     return false;
    530 
    531   static const LoadStoreMethod PossibleClasses[] = {
    532     {&AArch64::GPR64RegClass, AArch64::LSPair64_STR, AArch64::LS64_STR},
    533     {&AArch64::FPR64RegClass, AArch64::LSFPPair64_STR, AArch64::LSFP64_STR},
    534   };
    535   const unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
    536 
    537   emitFrameMemOps(/* isPrologue = */ true, MBB, MBBI, CSI, TRI,
    538                   PossibleClasses, NumClasses);
    539 
    540   return true;
    541 }
    542 
    543 bool
    544 AArch64FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
    545                                         MachineBasicBlock::iterator MBBI,
    546                                         const std::vector<CalleeSavedInfo> &CSI,
    547                                         const TargetRegisterInfo *TRI) const {
    548 
    549   if (CSI.empty())
    550     return false;
    551 
    552   static const LoadStoreMethod PossibleClasses[] = {
    553     {&AArch64::GPR64RegClass, AArch64::LSPair64_LDR, AArch64::LS64_LDR},
    554     {&AArch64::FPR64RegClass, AArch64::LSFPPair64_LDR, AArch64::LSFP64_LDR},
    555   };
    556   const unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
    557 
    558   emitFrameMemOps(/* isPrologue = */ false, MBB, MBBI, CSI, TRI,
    559                   PossibleClasses, NumClasses);
    560 
    561   return true;
    562 }
    563 
    564 bool
    565 AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
    566   const MachineFrameInfo *MFI = MF.getFrameInfo();
    567   const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo();
    568 
    569   // This is a decision of ABI compliance. The AArch64 PCS gives various options
    570   // for conformance, and even at the most stringent level more or less permits
    571   // elimination for leaf functions because there's no loss of functionality
    572   // (for debugging etc)..
    573   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->hasCalls())
    574     return true;
    575 
    576   // The following are hard-limits: incorrect code will be generated if we try
    577   // to omit the frame.
    578   return (RI->needsStackRealignment(MF) ||
    579           MFI->hasVarSizedObjects() ||
    580           MFI->isFrameAddressTaken());
    581 }
    582 
    583 bool
    584 AArch64FrameLowering::useFPForAddressing(const MachineFunction &MF) const {
    585   return MF.getFrameInfo()->hasVarSizedObjects();
    586 }
    587 
    588 bool
    589 AArch64FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
    590   const MachineFrameInfo *MFI = MF.getFrameInfo();
    591 
    592   // Of the various reasons for having a frame pointer, it's actually only
    593   // variable-sized objects that prevent reservation of a call frame.
    594   return !(hasFP(MF) && MFI->hasVarSizedObjects());
    595 }
    596 
    597 void
    598 AArch64FrameLowering::eliminateCallFramePseudoInstr(
    599                                 MachineFunction &MF,
    600                                 MachineBasicBlock &MBB,
    601                                 MachineBasicBlock::iterator MI) const {
    602   const AArch64InstrInfo &TII =
    603     *static_cast<const AArch64InstrInfo *>(MF.getTarget().getInstrInfo());
    604   DebugLoc dl = MI->getDebugLoc();
    605   int Opcode = MI->getOpcode();
    606   bool IsDestroy = Opcode == TII.getCallFrameDestroyOpcode();
    607   uint64_t CalleePopAmount = IsDestroy ? MI->getOperand(1).getImm() : 0;
    608 
    609   if (!hasReservedCallFrame(MF)) {
    610     unsigned Align = getStackAlignment();
    611 
    612     int64_t Amount = MI->getOperand(0).getImm();
    613     Amount = RoundUpToAlignment(Amount, Align);
    614     if (!IsDestroy) Amount = -Amount;
    615 
    616     // N.b. if CalleePopAmount is valid but zero (i.e. callee would pop, but it
    617     // doesn't have to pop anything), then the first operand will be zero too so
    618     // this adjustment is a no-op.
    619     if (CalleePopAmount == 0) {
    620       // FIXME: in-function stack adjustment for calls is limited to 12-bits
    621       // because there's no guaranteed temporary register available. Mostly call
    622       // frames will be allocated at the start of a function so this is OK, but
    623       // it is a limitation that needs dealing with.
    624       assert(Amount > -0xfff && Amount < 0xfff && "call frame too large");
    625       emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, Amount);
    626     }
    627   } else if (CalleePopAmount != 0) {
    628     // If the calling convention demands that the callee pops arguments from the
    629     // stack, we want to add it back if we have a reserved call frame.
    630     assert(CalleePopAmount < 0xfff && "call frame too large");
    631     emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, -CalleePopAmount);
    632   }
    633 
    634   MBB.erase(MI);
    635 }
    636