| /dalvik/vm/compiler/codegen/x86/ |
| NcgAot.h | 31 ConditionCode cc, const char* target,
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| NcgAot.cpp | 123 ConditionCode cc, const char* target,
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| Lower.h | 661 void conditional_move_reg_to_reg(OpndSize size, ConditionCode cc, int reg1, bool isPhysical1, int reg, bool isPhysical);
677 void conditional_jump(ConditionCode cc, const char* target, bool isShortTerm);
679 void conditional_jump_int(ConditionCode cc, int target, OpndSize size);
798 ConditionCode code_excep, ConditionCode code_okay,
[all...] |
| LowerJump.cpp | 531 void conditional_jump(ConditionCode cc, const char* target, bool isShortTerm) {
587 void conditional_jump_int(ConditionCode cc, int target, OpndSize size) {
930 int common_if(s4 tmp, ConditionCode cc_next, ConditionCode cc) {
[all...] |
| /art/compiler/dex/quick/mips/ |
| codegen_mips.h | 114 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
140 LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
141 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
142 LIR* OpCondBranch(ConditionCode cc, LIR* target);
143 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
145 LIR* OpIT(ConditionCode cond, const char* guide);
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| int_mips.cc | 64 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, int src1, int src2,
112 LOG(FATAL) << "No support for ConditionCode: " << cond;
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, int reg,
220 LIR* MipsMir2Lir::GenRegMemCheck(ConditionCode c_code,
312 LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
323 LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) {
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| utility_mips.cc | 663 LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
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| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 113 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
139 LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
140 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
141 LIR* OpCondBranch(ConditionCode cc, LIR* target);
142 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
144 LIR* OpIT(ConditionCode cond, const char* guide);
173 ArmConditionCode ArmConditionEncoding(ConditionCode code);
181 ConditionCode ccode);
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| int_arm.cc | 27 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, int src1,
43 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) {
121 int64_t val, ConditionCode ccode) {
136 ConditionCode condition;
251 ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]);
311 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, int reg, int check_value,
462 LIR* ArmMir2Lir::GenRegMemCheck(ConditionCode c_code,
600 LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
[all...] |
| fp_arm.cc | 197 ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]);
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| target_arm.cc | 196 ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode) {
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| /art/compiler/dex/quick/x86/ |
| codegen_x86.h | 114 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
140 LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
141 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
142 LIR* OpCondBranch(ConditionCode cc, LIR* target);
143 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
145 LIR* OpIT(ConditionCode cond, const char* guide);
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| int_x86.cc | 29 LIR* X86Mir2Lir::GenRegMemCheck(ConditionCode c_code,
66 X86ConditionCode X86ConditionEncoding(ConditionCode cond) {
88 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, int src1, int src2,
98 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, int reg,
176 ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]);
293 LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
304 LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) {
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| fp_x86.cc | 306 ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]);
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| x86_lir.h | 439 extern X86ConditionCode X86ConditionEncoding(ConditionCode cond);
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| utility_x86.cc | 108 LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
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| /art/compiler/dex/quick/ |
| mir_to_lir.h | 281 ConditionCode FlipComparisonOrder(ConditionCode before);
386 LIR* GenCheck(ConditionCode c_code, ThrowKind kind);
387 LIR* GenImmedCheck(ConditionCode c_code, int reg, int imm_val,
390 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2,
612 virtual LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base,
[all...] |
| gen_common.cc | 45 LIR* Mir2Lir::GenCheck(ConditionCode c_code, ThrowKind kind) {
54 LIR* Mir2Lir::GenImmedCheck(ConditionCode c_code, int reg, int imm_val, ThrowKind kind) {
77 LIR* Mir2Lir::GenRegRegCheck(ConditionCode c_code, int reg1, int reg2,
89 ConditionCode cond;
110 cond = static_cast<ConditionCode>(0);
142 ConditionCode cond;
164 cond = static_cast<ConditionCode>(0);
[all...] |
| codegen_util.cc | [all...] |
| /dalvik/vm/compiler/codegen/x86/libenc/ |
| encoder.h | 132 typedef enum ConditionCode {
165 } ConditionCode;
557 ENCODER_DECLARE_EXPORT char * cmov(char * stream, ConditionCode cc, const R_Opnd & r, const RM_Opnd & rm, Opnd_Size sz = size_platf);
558 ENCODER_DECLARE_EXPORT char * setcc(char * stream, ConditionCode cc, const RM_Opnd & rm8);
584 ENCODER_DECLARE_EXPORT char * branch8(char * stream, ConditionCode cc, const Imm_Opnd & imm, InstrPrefix prefix = no_prefix);
587 ENCODER_DECLARE_EXPORT char * branch32(char * stream, ConditionCode cc, const Imm_Opnd & imm, InstrPrefix prefix = no_prefix);
590 //char * branch(char * stream, ConditionCode cc, const char * target, InstrPrefix prefix = no_prefix);
593 ENCODER_DECLARE_EXPORT char * branch(char * stream, ConditionCode cc, I_32 disp, InstrPrefix prefix = no_prefix);
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| enc_wrapper.h | 92 typedef enum ConditionCode {
125 } ConditionCode;
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| encoder.inl | 536 ENCODER_DECLARE_EXPORT char *cmov(char * stream, ConditionCode cc, const R_Opnd & r, const RM_Opnd & rm, Opnd_Size sz) {
543 ENCODER_DECLARE_EXPORT char * setcc(char * stream, ConditionCode cc, const RM_Opnd & rm8) {
638 ENCODER_DECLARE_EXPORT char * branch8(char * stream, ConditionCode cond,
653 ENCODER_DECLARE_EXPORT char * branch32(char * stream, ConditionCode cond,
669 ENCODER_DECLARE_EXPORT char * branch(char * stream, ConditionCode cc, const char * target, InstrPrefix prefix) {
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| /art/compiler/dex/portable/ |
| mir_to_gbc.h | 108 ::llvm::Value* ConvertCompare(ConditionCode cc,
110 void ConvertCompareAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
112 void ConvertCompareZeroAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
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| mir_to_gbc.cc | 296 ::llvm::Value* MirConverter::ConvertCompare(ConditionCode cc,
313 ConditionCode cc, RegLocation rl_src1, RegLocation rl_src2) {
328 MIR* mir, ConditionCode cc, RegLocation rl_src1) {
[all...] |
| /art/compiler/dex/ |
| compiler_enums.h | 198 enum ConditionCode {
219 std::ostream& operator<<(std::ostream& os, const ConditionCode& kind);
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