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      1 //===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines a wrapper around MCSchedModel that allows the interface to
     11 // benefit from information currently only available in TargetInstrInfo.
     12 // Ideally, the scheduling interface would be fully defined in the MC layer.
     13 //
     14 //===----------------------------------------------------------------------===//
     15 
     16 #ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
     17 #define LLVM_CODEGEN_TARGETSCHEDULE_H
     18 
     19 #include "llvm/ADT/SmallVector.h"
     20 #include "llvm/MC/MCInstrItineraries.h"
     21 #include "llvm/MC/MCSchedule.h"
     22 #include "llvm/Target/TargetSubtargetInfo.h"
     23 
     24 namespace llvm {
     25 
     26 class TargetRegisterInfo;
     27 class TargetSubtargetInfo;
     28 class TargetInstrInfo;
     29 class MachineInstr;
     30 
     31 /// Provide an instruction scheduling machine model to CodeGen passes.
     32 class TargetSchedModel {
     33   // For efficiency, hold a copy of the statically defined MCSchedModel for this
     34   // processor.
     35   MCSchedModel SchedModel;
     36   InstrItineraryData InstrItins;
     37   const TargetSubtargetInfo *STI;
     38   const TargetInstrInfo *TII;
     39 
     40   SmallVector<unsigned, 16> ResourceFactors;
     41   unsigned MicroOpFactor; // Multiply to normalize microops to resource units.
     42   unsigned ResourceLCM;   // Resource units per cycle. Latency normalization factor.
     43 public:
     44   TargetSchedModel(): STI(0), TII(0) {}
     45 
     46   /// \brief Initialize the machine model for instruction scheduling.
     47   ///
     48   /// The machine model API keeps a copy of the top-level MCSchedModel table
     49   /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
     50   /// dynamic properties.
     51   void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
     52             const TargetInstrInfo *tii);
     53 
     54   /// Return the MCSchedClassDesc for this instruction.
     55   const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
     56 
     57   /// \brief TargetInstrInfo getter.
     58   const TargetInstrInfo *getInstrInfo() const { return TII; }
     59 
     60   /// \brief Return true if this machine model includes an instruction-level
     61   /// scheduling model.
     62   ///
     63   /// This is more detailed than the course grain IssueWidth and default
     64   /// latency properties, but separate from the per-cycle itinerary data.
     65   bool hasInstrSchedModel() const;
     66 
     67   const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
     68 
     69   /// \brief Return true if this machine model includes cycle-to-cycle itinerary
     70   /// data.
     71   ///
     72   /// This models scheduling at each stage in the processor pipeline.
     73   bool hasInstrItineraries() const;
     74 
     75   const InstrItineraryData *getInstrItineraries() const {
     76     if (hasInstrItineraries())
     77       return &InstrItins;
     78     return 0;
     79   }
     80 
     81   /// \brief Identify the processor corresponding to the current subtarget.
     82   unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
     83 
     84   /// \brief Maximum number of micro-ops that may be scheduled per cycle.
     85   unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
     86 
     87   /// \brief Return the number of issue slots required for this MI.
     88   unsigned getNumMicroOps(const MachineInstr *MI,
     89                           const MCSchedClassDesc *SC = 0) const;
     90 
     91   /// \brief Get the number of kinds of resources for this target.
     92   unsigned getNumProcResourceKinds() const {
     93     return SchedModel.getNumProcResourceKinds();
     94   }
     95 
     96   /// \brief Get a processor resource by ID for convenience.
     97   const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
     98     return SchedModel.getProcResource(PIdx);
     99   }
    100 
    101   typedef const MCWriteProcResEntry *ProcResIter;
    102 
    103   // \brief Get an iterator into the processor resources consumed by this
    104   // scheduling class.
    105   ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
    106     // The subtarget holds a single resource table for all processors.
    107     return STI->getWriteProcResBegin(SC);
    108   }
    109   ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
    110     return STI->getWriteProcResEnd(SC);
    111   }
    112 
    113   /// \brief Multiply the number of units consumed for a resource by this factor
    114   /// to normalize it relative to other resources.
    115   unsigned getResourceFactor(unsigned ResIdx) const {
    116     return ResourceFactors[ResIdx];
    117   }
    118 
    119   /// \brief Multiply number of micro-ops by this factor to normalize it
    120   /// relative to other resources.
    121   unsigned getMicroOpFactor() const {
    122     return MicroOpFactor;
    123   }
    124 
    125   /// \brief Multiply cycle count by this factor to normalize it relative to
    126   /// other resources. This is the number of resource units per cycle.
    127   unsigned getLatencyFactor() const {
    128     return ResourceLCM;
    129   }
    130 
    131   /// \brief Number of micro-ops that may be buffered for OOO execution.
    132   unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
    133 
    134   /// \brief Number of resource units that may be buffered for OOO execution.
    135   /// \return The buffer size in resource units or -1 for unlimited.
    136   int getResourceBufferSize(unsigned PIdx) const {
    137     return SchedModel.getProcResource(PIdx)->BufferSize;
    138   }
    139 
    140   /// \brief Compute operand latency based on the available machine model.
    141   ///
    142   /// Compute and return the latency of the given data dependent def and use
    143   /// when the operand indices are already known. UseMI may be NULL for an
    144   /// unknown user.
    145   unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
    146                                  const MachineInstr *UseMI, unsigned UseOperIdx)
    147     const;
    148 
    149   /// \brief Compute the instruction latency based on the available machine
    150   /// model.
    151   ///
    152   /// Compute and return the expected latency of this instruction independent of
    153   /// a particular use. computeOperandLatency is the prefered API, but this is
    154   /// occasionally useful to help estimate instruction cost.
    155   unsigned computeInstrLatency(const MachineInstr *MI) const;
    156 
    157   /// \brief Output dependency latency of a pair of defs of the same register.
    158   ///
    159   /// This is typically one cycle.
    160   unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
    161                                 const MachineInstr *DepMI) const;
    162 };
    163 
    164 } // namespace llvm
    165 
    166 #endif
    167