| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 171 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-ia32.cc | 342 __ fmul(3);
|
| test-disasm-x64.cc | 324 __ fmul(3);
|
| /external/llvm/docs/ |
| NVPTXUsage.rst | 51 %mul = fmul float %x, %y
|
| /external/llvm/include/llvm/Analysis/ |
| InstructionSimplify.h | 76 /// Given operands for an FMul, see if we can fold the result. If not, this
|
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 43 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
44 setOperationAction(ISD::FMUL, MVT::v2f32, Expand);
745 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
765 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
[all...] |
| SIInstructions.td | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 171 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
|
| /external/proguard/src/proguard/classfile/instruction/ |
| InstructionConstants.java | 342 "fmul",
|
| /external/v8/test/cctest/ |
| test-disasm-ia32.cc | 360 __ fmul(3);
|
| test-disasm-x64.cc | 340 __ fmul(3);
|
| /external/llvm/lib/AsmParser/ |
| LLLexer.cpp | 645 INSTKEYWORD(mul, Mul); INSTKEYWORD(fmul, FMul);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 202 case ISD::FMUL:
731 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
|
| /external/llvm/test/MC/X86/ |
| x86-32.s | 325 // CHECK: fmul %st(0)
327 fmul %st(0), %st
|
| /prebuilts/gcc/darwin-x86/host/i686-apple-darwin-4.2.1/include/gcc/darwin/4.2/ |
| ppc_intrinsics.h | 618 * fmul - Floating Multiply (Double-Precision)
627 __asm__ ("fmul %0, %1, %2"
|
| /external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
| assyntax.h | 751 #define FMUL2(a, b) CHOICE(fmul ARG2(a,b), fmul ARG2(a,b), fmul ARG2(b,a))
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrNEON.td | 196 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
256 (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
259 (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
[all...] |
| AArch64InstrInfo.td | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrVFP.td | 310 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
316 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
325 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
330 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
373 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
375 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
[all...] |
| /external/mesa3d/src/mesa/x86/ |
| assyntax.h | 751 #define FMUL2(a, b) CHOICE(fmul ARG2(a,b), fmul ARG2(a,b), fmul ARG2(b,a))
[all...] |
| /external/elfutils/libcpu/defs/ |
| i386 | 204 11011000,11001{freg}:fmul {freg},%st
205 11011100,11001{freg}:fmul %st,{freg}
206 11011{D}00,{mod}001{r_m}:fmul{D} {mod}{r_m}
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 106 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
368 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 392 if (I->getOpcode() == Instruction::FMul) {
449 if (I0->getOpcode() == Instruction::FMul)
820 // <C, V> "fmul V, C" false
[all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | 740 case Instruction::FMul:
854 case Instruction::FMul:
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | [all...] |
