1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This file was originally auto-generated from a GPU register header file and 10 // all the instruction definitions were originally commented out. Instructions 11 // that are not yet supported remain commented out. 12 //===----------------------------------------------------------------------===// 13 14 class InterpSlots { 15 int P0 = 2; 16 int P10 = 0; 17 int P20 = 1; 18 } 19 def INTERP : InterpSlots; 20 21 def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23 } 24 25 def isSI : Predicate<"Subtarget.getGeneration() " 26 "== AMDGPUSubtarget::SOUTHERN_ISLANDS">; 27 28 let Predicates = [isSI] in { 29 30 let neverHasSideEffects = 1 in { 31 32 let isMoveImm = 1 in { 33 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 34 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 35 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 36 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 37 } // End isMoveImm = 1 38 39 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 40 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 41 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 42 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 43 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 44 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 45 } // End neverHasSideEffects = 1 46 47 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 48 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 49 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 50 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 51 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 52 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 53 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 54 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 55 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 56 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 57 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 58 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 59 //def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 60 //def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 61 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 62 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 63 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 64 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 65 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 66 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 67 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 68 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 69 70 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 71 72 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 73 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 74 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 75 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 76 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 77 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 78 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 79 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 80 81 } // End hasSideEffects = 1 82 83 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 84 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 85 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 86 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 87 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 88 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 89 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 90 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 91 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 92 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 93 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 94 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 95 96 /* 97 This instruction is disabled for now until we can figure out how to teach 98 the instruction selector to correctly use the S_CMP* vs V_CMP* 99 instructions. 100 101 When this instruction is enabled the code generator sometimes produces this 102 invalid sequence: 103 104 SCC = S_CMPK_EQ_I32 SGPR0, imm 105 VCC = COPY SCC 106 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 107 108 def S_CMPK_EQ_I32 : SOPK < 109 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 110 "S_CMPK_EQ_I32", 111 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 112 >; 113 */ 114 115 let isCompare = 1 in { 116 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 117 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 118 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 119 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 120 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 121 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 122 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 123 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 124 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 125 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 126 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 127 } // End isCompare = 1 128 129 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 130 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 131 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 132 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 133 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 134 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 135 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 136 //def EXP : EXP_ <0x00000000, "EXP", []>; 137 138 let isCompare = 1 in { 139 140 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 141 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_LT>; 142 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_EQ>; 143 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_LE>; 144 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_GT>; 145 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", f32, COND_NE>; 146 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_GE>; 147 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32">; 148 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32">; 149 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 150 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 151 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 152 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 153 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_NE>; 154 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 155 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 156 157 let hasSideEffects = 1, Defs = [EXEC] in { 158 159 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 160 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 161 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 162 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 163 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 164 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 165 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 166 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 167 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 168 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 169 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 170 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 171 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 172 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 173 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 174 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 175 176 } // End hasSideEffects = 1, Defs = [EXEC] 177 178 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 179 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_LT>; 180 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_EQ>; 181 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_LE>; 182 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_GT>; 183 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 184 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_GE>; 185 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64">; 186 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64">; 187 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 188 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 189 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 190 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 191 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_NE>; 192 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 193 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 194 195 let hasSideEffects = 1, Defs = [EXEC] in { 196 197 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 198 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 199 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 200 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 201 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 202 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 203 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 204 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 205 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 206 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 207 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 208 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 209 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 210 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 211 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 212 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 213 214 } // End hasSideEffects = 1, Defs = [EXEC] 215 216 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 217 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 218 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 219 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 220 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 221 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 222 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 223 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 224 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 225 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 226 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 227 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 228 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 229 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 230 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 231 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 232 233 let hasSideEffects = 1, Defs = [EXEC] in { 234 235 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 236 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 237 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 238 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 239 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 240 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 241 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 242 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 243 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 244 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 245 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 246 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 247 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 248 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 249 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 250 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 251 252 } // End hasSideEffects = 1, Defs = [EXEC] 253 254 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 255 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 256 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 257 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 258 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 259 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 260 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 261 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 262 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 263 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 264 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 265 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 266 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 267 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 268 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 269 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 270 271 let hasSideEffects = 1, Defs = [EXEC] in { 272 273 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 274 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 275 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 276 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 277 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 278 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 279 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 280 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 281 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 282 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 283 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 284 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 285 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 286 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 287 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 288 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 289 290 } // End hasSideEffects = 1, Defs = [EXEC] 291 292 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 293 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_LT>; 294 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 295 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_LE>; 296 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_GT>; 297 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 298 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_GE>; 299 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 300 301 let hasSideEffects = 1, Defs = [EXEC] in { 302 303 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 304 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 305 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 306 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 307 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 308 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 309 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 310 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 311 312 } // End hasSideEffects = 1, Defs = [EXEC] 313 314 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 315 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64">; 316 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64">; 317 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64">; 318 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64">; 319 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64">; 320 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64">; 321 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 322 323 let hasSideEffects = 1, Defs = [EXEC] in { 324 325 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 326 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 327 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 328 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 329 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 330 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 331 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 332 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 333 334 } // End hasSideEffects = 1, Defs = [EXEC] 335 336 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 337 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32">; 338 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32">; 339 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32">; 340 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32">; 341 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32">; 342 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32">; 343 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 344 345 let hasSideEffects = 1, Defs = [EXEC] in { 346 347 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 348 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 349 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 350 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 351 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 352 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 353 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 354 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 355 356 } // End hasSideEffects = 1, Defs = [EXEC] 357 358 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 359 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64">; 360 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64">; 361 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64">; 362 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64">; 363 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64">; 364 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64">; 365 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 366 367 let hasSideEffects = 1, Defs = [EXEC] in { 368 369 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 370 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 371 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 372 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 373 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 374 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 375 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 376 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 377 378 } // End hasSideEffects = 1, Defs = [EXEC] 379 380 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 381 382 let hasSideEffects = 1, Defs = [EXEC] in { 383 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 384 } // End hasSideEffects = 1, Defs = [EXEC] 385 386 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 387 388 let hasSideEffects = 1, Defs = [EXEC] in { 389 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 390 } // End hasSideEffects = 1, Defs = [EXEC] 391 392 } // End isCompare = 1 393 394 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; 395 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>; 396 397 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 398 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 399 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 400 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 401 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 402 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 403 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 404 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 405 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; 406 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>; 407 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>; 408 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>; 409 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 410 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 411 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 412 //def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>; 413 //def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>; 414 415 def BUFFER_STORE_DWORD : MUBUF_Store_Helper < 416 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32 417 >; 418 419 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 420 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, i64 421 >; 422 423 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 424 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128, v4i32 425 >; 426 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 427 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 428 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 429 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 430 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 431 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 432 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 433 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 434 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 435 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 436 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 437 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 438 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 439 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 440 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 441 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 442 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 443 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 444 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 445 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 446 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 447 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 448 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 449 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 450 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 451 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 452 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 453 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 454 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 455 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 456 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 457 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 458 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 459 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 460 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 461 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 462 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 463 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 464 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 465 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 466 //def TBUFFER_STORE_FORMAT_X : MTBUF_ <0x00000004, "TBUFFER_STORE_FORMAT_X", []>; 467 //def TBUFFER_STORE_FORMAT_XY : MTBUF_ <0x00000005, "TBUFFER_STORE_FORMAT_XY", []>; 468 //def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>; 469 //def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>; 470 471 let mayLoad = 1 in { 472 473 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SReg_32>; 474 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 475 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 476 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 477 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 478 479 defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 480 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SReg_32 481 >; 482 483 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 484 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 485 >; 486 487 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 488 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 489 >; 490 491 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 492 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 493 >; 494 495 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 496 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 497 >; 498 499 } // mayLoad = 1 500 501 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 502 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 503 //def IMAGE_LOAD : MIMG_NoPattern_ <"IMAGE_LOAD", 0x00000000>; 504 def IMAGE_LOAD_MIP : MIMG_NoSampler_Helper <0x00000001, "IMAGE_LOAD_MIP">; 505 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 506 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 507 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 508 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 509 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 510 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 511 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 512 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 513 def IMAGE_GET_RESINFO : MIMG_NoSampler_Helper <0x0000000e, "IMAGE_GET_RESINFO">; 514 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 515 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 516 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 517 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 518 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 519 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 520 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 521 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 522 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 523 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 524 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 525 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 526 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 527 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 528 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 529 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 530 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 531 def IMAGE_SAMPLE : MIMG_Sampler_Helper <0x00000020, "IMAGE_SAMPLE">; 532 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 533 def IMAGE_SAMPLE_D : MIMG_Sampler_Helper <0x00000022, "IMAGE_SAMPLE_D">; 534 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 535 def IMAGE_SAMPLE_L : MIMG_Sampler_Helper <0x00000024, "IMAGE_SAMPLE_L">; 536 def IMAGE_SAMPLE_B : MIMG_Sampler_Helper <0x00000025, "IMAGE_SAMPLE_B">; 537 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 538 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 539 def IMAGE_SAMPLE_C : MIMG_Sampler_Helper <0x00000028, "IMAGE_SAMPLE_C">; 540 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 541 def IMAGE_SAMPLE_C_D : MIMG_Sampler_Helper <0x0000002a, "IMAGE_SAMPLE_C_D">; 542 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 543 def IMAGE_SAMPLE_C_L : MIMG_Sampler_Helper <0x0000002c, "IMAGE_SAMPLE_C_L">; 544 def IMAGE_SAMPLE_C_B : MIMG_Sampler_Helper <0x0000002d, "IMAGE_SAMPLE_C_B">; 545 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 546 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 547 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 548 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 549 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 550 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 551 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 552 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 553 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 554 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 555 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 556 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 557 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 558 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 559 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 560 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 561 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 562 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 563 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 564 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 565 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 566 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 567 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 568 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 569 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 570 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 571 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 572 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 573 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 574 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 575 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 576 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 577 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 578 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 579 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 580 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 581 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 582 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 583 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 584 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 585 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 586 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 587 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 588 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 589 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 590 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 591 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 592 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 593 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 594 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 595 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 596 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 597 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 598 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 599 600 601 let neverHasSideEffects = 1, isMoveImm = 1 in { 602 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 603 } // End neverHasSideEffects = 1, isMoveImm = 1 604 605 defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 606 //defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>; 607 //defm V_CVT_F64_I32 : VOP1_64 <0x00000004, "V_CVT_F64_I32", []>; 608 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 609 [(set f32:$dst, (sint_to_fp i32:$src0))] 610 >; 611 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", 612 [(set f32:$dst, (uint_to_fp i32:$src0))] 613 >; 614 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", []>; 615 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 616 [(set i32:$dst, (fp_to_sint f32:$src0))] 617 >; 618 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 619 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 620 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 621 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 622 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 623 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 624 //defm V_CVT_F32_F64 : VOP1_32 <0x0000000f, "V_CVT_F32_F64", []>; 625 //defm V_CVT_F64_F32 : VOP1_64 <0x00000010, "V_CVT_F64_F32", []>; 626 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 627 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 628 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 629 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 630 //defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 631 //defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 632 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 633 [(set f32:$dst, (AMDGPUfract f32:$src0))] 634 >; 635 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", 636 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] 637 >; 638 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 639 [(set f32:$dst, (fceil f32:$src0))] 640 >; 641 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 642 [(set f32:$dst, (frint f32:$src0))] 643 >; 644 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 645 [(set f32:$dst, (ffloor f32:$src0))] 646 >; 647 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 648 [(set f32:$dst, (fexp2 f32:$src0))] 649 >; 650 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 651 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 652 [(set f32:$dst, (flog2 f32:$src0))] 653 >; 654 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 655 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 656 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 657 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 658 >; 659 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 660 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 661 defm V_RSQ_LEGACY_F32 : VOP1_32 < 662 0x0000002d, "V_RSQ_LEGACY_F32", 663 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] 664 >; 665 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 666 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", 667 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))] 668 >; 669 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 670 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 671 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 672 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", 673 [(set f32:$dst, (fsqrt f32:$src0))] 674 >; 675 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", 676 [(set f64:$dst, (fsqrt f64:$src0))] 677 >; 678 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 679 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 680 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 681 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 682 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 683 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 684 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 685 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 686 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 687 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 688 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 689 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 690 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 691 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 692 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 693 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 694 695 def V_INTERP_P1_F32 : VINTRP < 696 0x00000000, 697 (outs VReg_32:$dst), 698 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 699 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 700 []> { 701 let DisableEncoding = "$m0"; 702 } 703 704 def V_INTERP_P2_F32 : VINTRP < 705 0x00000001, 706 (outs VReg_32:$dst), 707 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 708 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 709 []> { 710 711 let Constraints = "$src0 = $dst"; 712 let DisableEncoding = "$src0,$m0"; 713 714 } 715 716 def V_INTERP_MOV_F32 : VINTRP < 717 0x00000002, 718 (outs VReg_32:$dst), 719 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 720 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 721 []> { 722 let DisableEncoding = "$m0"; 723 } 724 725 //def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 726 727 let isTerminator = 1 in { 728 729 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 730 [(IL_retflag)]> { 731 let SIMM16 = 0; 732 let isBarrier = 1; 733 let hasCtrlDep = 1; 734 } 735 736 let isBranch = 1 in { 737 def S_BRANCH : SOPP < 738 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 739 [(br bb:$target)]> { 740 let isBarrier = 1; 741 } 742 743 let DisableEncoding = "$scc" in { 744 def S_CBRANCH_SCC0 : SOPP < 745 0x00000004, (ins brtarget:$target, SCCReg:$scc), 746 "S_CBRANCH_SCC0 $target", [] 747 >; 748 def S_CBRANCH_SCC1 : SOPP < 749 0x00000005, (ins brtarget:$target, SCCReg:$scc), 750 "S_CBRANCH_SCC1 $target", 751 [] 752 >; 753 } // End DisableEncoding = "$scc" 754 755 def S_CBRANCH_VCCZ : SOPP < 756 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 757 "S_CBRANCH_VCCZ $target", 758 [] 759 >; 760 def S_CBRANCH_VCCNZ : SOPP < 761 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 762 "S_CBRANCH_VCCNZ $target", 763 [] 764 >; 765 766 let DisableEncoding = "$exec" in { 767 def S_CBRANCH_EXECZ : SOPP < 768 0x00000008, (ins brtarget:$target, EXECReg:$exec), 769 "S_CBRANCH_EXECZ $target", 770 [] 771 >; 772 def S_CBRANCH_EXECNZ : SOPP < 773 0x00000009, (ins brtarget:$target, EXECReg:$exec), 774 "S_CBRANCH_EXECNZ $target", 775 [] 776 >; 777 } // End DisableEncoding = "$exec" 778 779 780 } // End isBranch = 1 781 } // End isTerminator = 1 782 783 let hasSideEffects = 1 in { 784 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", 785 [(int_AMDGPU_barrier_local)] 786 > { 787 let SIMM16 = 0; 788 let isBarrier = 1; 789 let hasCtrlDep = 1; 790 let mayLoad = 1; 791 let mayStore = 1; 792 } 793 794 def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16", 795 [] 796 >; 797 } // End hasSideEffects 798 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 799 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 800 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 801 //def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>; 802 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 803 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 804 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 805 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 806 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 807 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 808 809 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 810 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 811 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 812 [] 813 >{ 814 let DisableEncoding = "$vcc"; 815 } 816 817 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 818 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 819 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 820 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 821 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] 822 >; 823 824 //f32 pattern for V_CNDMASK_B32_e64 825 def : Pat < 826 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 827 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 828 >; 829 830 //use two V_CNDMASK_B32_e64 instructions for f64 831 def : Pat < 832 (f64 (select i1:$src2, f64:$src1, f64:$src0)), 833 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 834 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0), 835 (EXTRACT_SUBREG $src1, sub0), 836 $src2), sub0), 837 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1), 838 (EXTRACT_SUBREG $src1, sub1), 839 $src2), sub1) 840 >; 841 842 defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 843 defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 844 845 let isCommutable = 1 in { 846 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 847 [(set f32:$dst, (fadd f32:$src0, f32:$src1))] 848 >; 849 850 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 851 [(set f32:$dst, (fsub f32:$src0, f32:$src1))] 852 >; 853 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 854 } // End isCommutable = 1 855 856 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 857 858 let isCommutable = 1 in { 859 860 defm V_MUL_LEGACY_F32 : VOP2_32 < 861 0x00000007, "V_MUL_LEGACY_F32", 862 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] 863 >; 864 865 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 866 [(set f32:$dst, (fmul f32:$src0, f32:$src1))] 867 >; 868 869 870 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", 871 [(set i32:$dst, (mul I24:$src0, I24:$src1))] 872 >; 873 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 874 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", 875 [(set i32:$dst, (mul U24:$src0, U24:$src1))] 876 >; 877 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 878 879 880 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 881 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] 882 >; 883 884 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 885 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] 886 >; 887 888 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 889 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 890 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", 891 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] 892 >; 893 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", 894 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] 895 >; 896 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", 897 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] 898 >; 899 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", 900 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] 901 >; 902 903 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", 904 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 905 >; 906 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 907 908 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", 909 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 910 >; 911 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 912 913 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 914 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 915 >; 916 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 917 918 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 919 [(set i32:$dst, (and i32:$src0, i32:$src1))] 920 >; 921 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 922 [(set i32:$dst, (or i32:$src0, i32:$src1))] 923 >; 924 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 925 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 926 >; 927 928 } // End isCommutable = 1 929 930 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 931 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 932 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 933 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 934 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 935 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 936 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 937 938 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 939 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", 940 [(set i32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))] 941 >; 942 943 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", 944 [(set i32:$dst, (sub i32:$src0, i32:$src1))] 945 >; 946 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">; 947 948 let Uses = [VCC] in { // Carry-out comes from VCC 949 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>; 950 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>; 951 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">; 952 } // End Uses = [VCC] 953 } // End isCommutable = 1, Defs = [VCC] 954 955 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 956 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 957 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 958 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 959 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 960 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] 961 >; 962 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 963 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 964 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 965 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 966 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 967 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 968 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 969 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 970 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 971 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 972 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 973 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 974 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 975 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 976 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 977 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 978 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 979 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 980 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 981 982 let neverHasSideEffects = 1 in { 983 984 def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 985 def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 986 def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", 987 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))] 988 >; 989 def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", 990 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))] 991 >; 992 993 } // End neverHasSideEffects 994 def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 995 def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 996 def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 997 def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 998 def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 999 def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 1000 def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 1001 defm : BFIPatterns <V_BFI_B32>; 1002 def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>; 1003 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>; 1004 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 1005 def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 1006 def : ROTRPattern <V_ALIGNBIT_B32>; 1007 1008 def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 1009 def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 1010 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 1011 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 1012 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 1013 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 1014 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 1015 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 1016 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 1017 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 1018 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 1019 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 1020 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 1021 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 1022 def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 1023 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 1024 def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 1025 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 1026 1027 def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64", 1028 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1029 >; 1030 def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64", 1031 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1032 >; 1033 def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64", 1034 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1035 >; 1036 1037 let isCommutable = 1 in { 1038 1039 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 1040 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 1041 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 1042 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 1043 1044 } // isCommutable = 1 1045 1046 def : Pat < 1047 (fadd f64:$src0, f64:$src1), 1048 (V_ADD_F64 $src0, $src1, (i64 0)) 1049 >; 1050 1051 def : Pat < 1052 (fmul f64:$src0, f64:$src1), 1053 (V_MUL_F64 $src0, $src1, (i64 0)) 1054 >; 1055 1056 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 1057 1058 let isCommutable = 1 in { 1059 1060 def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 1061 def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 1062 def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 1063 def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 1064 1065 } // isCommutable = 1 1066 1067 def : Pat < 1068 (mul i32:$src0, i32:$src1), 1069 (V_MUL_LO_I32 $src0, $src1, (i32 0)) 1070 >; 1071 1072 def : Pat < 1073 (mulhu i32:$src0, i32:$src1), 1074 (V_MUL_HI_U32 $src0, $src1, (i32 0)) 1075 >; 1076 1077 def : Pat < 1078 (mulhs i32:$src0, i32:$src1), 1079 (V_MUL_HI_I32 $src0, $src1, (i32 0)) 1080 >; 1081 1082 def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1083 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1084 def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1085 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1086 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1087 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1088 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1089 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1090 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 1091 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 1092 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", []>; 1093 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", []>; 1094 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>; 1095 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>; 1096 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 1097 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 1098 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 1099 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 1100 1101 def S_CSELECT_B32 : SOP2 < 1102 0x0000000a, (outs SReg_32:$dst), 1103 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1104 [] 1105 >; 1106 1107 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1108 1109 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 1110 1111 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1112 [(set i64:$dst, (and i64:$src0, i64:$src1))] 1113 >; 1114 1115 def : Pat < 1116 (i1 (and i1:$src0, i1:$src1)), 1117 (S_AND_B64 $src0, $src1) 1118 >; 1119 1120 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 1121 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 1122 def : Pat < 1123 (i1 (or i1:$src0, i1:$src1)), 1124 (S_OR_B64 $src0, $src1) 1125 >; 1126 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 1127 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", []>; 1128 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1129 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1130 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1131 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1132 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1133 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1134 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1135 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1136 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1137 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1138 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", []>; 1139 def S_LSHL_B64 : SOP2_64 <0x0000001f, "S_LSHL_B64", []>; 1140 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", []>; 1141 def S_LSHR_B64 : SOP2_64 <0x00000021, "S_LSHR_B64", []>; 1142 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", []>; 1143 def S_ASHR_I64 : SOP2_64 <0x00000023, "S_ASHR_I64", []>; 1144 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1145 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1146 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1147 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1148 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1149 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1150 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1151 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1152 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1153 1154 let isCodeGenOnly = 1, isPseudo = 1 in { 1155 1156 def LOAD_CONST : AMDGPUShaderInst < 1157 (outs GPRF32:$dst), 1158 (ins i32imm:$src), 1159 "LOAD_CONST $dst, $src", 1160 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1161 >; 1162 1163 // SI Psuedo instructions. These are used by the CFG structurizer pass 1164 // and should be lowered to ISA instructions prior to codegen. 1165 1166 let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1167 Uses = [EXEC], Defs = [EXEC] in { 1168 1169 let isBranch = 1, isTerminator = 1 in { 1170 1171 def SI_IF : InstSI < 1172 (outs SReg_64:$dst), 1173 (ins SReg_64:$vcc, brtarget:$target), 1174 "SI_IF $dst, $vcc, $target", 1175 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1176 >; 1177 1178 def SI_ELSE : InstSI < 1179 (outs SReg_64:$dst), 1180 (ins SReg_64:$src, brtarget:$target), 1181 "SI_ELSE $dst, $src, $target", 1182 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> { 1183 1184 let Constraints = "$src = $dst"; 1185 } 1186 1187 def SI_LOOP : InstSI < 1188 (outs), 1189 (ins SReg_64:$saved, brtarget:$target), 1190 "SI_LOOP $saved, $target", 1191 [(int_SI_loop i64:$saved, bb:$target)] 1192 >; 1193 1194 } // end isBranch = 1, isTerminator = 1 1195 1196 def SI_BREAK : InstSI < 1197 (outs SReg_64:$dst), 1198 (ins SReg_64:$src), 1199 "SI_ELSE $dst, $src", 1200 [(set i64:$dst, (int_SI_break i64:$src))] 1201 >; 1202 1203 def SI_IF_BREAK : InstSI < 1204 (outs SReg_64:$dst), 1205 (ins SReg_64:$vcc, SReg_64:$src), 1206 "SI_IF_BREAK $dst, $vcc, $src", 1207 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1208 >; 1209 1210 def SI_ELSE_BREAK : InstSI < 1211 (outs SReg_64:$dst), 1212 (ins SReg_64:$src0, SReg_64:$src1), 1213 "SI_ELSE_BREAK $dst, $src0, $src1", 1214 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1215 >; 1216 1217 def SI_END_CF : InstSI < 1218 (outs), 1219 (ins SReg_64:$saved), 1220 "SI_END_CF $saved", 1221 [(int_SI_end_cf i64:$saved)] 1222 >; 1223 1224 def SI_KILL : InstSI < 1225 (outs), 1226 (ins VReg_32:$src), 1227 "SI_KIL $src", 1228 [(int_AMDGPU_kill f32:$src)] 1229 >; 1230 1231 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1232 // Uses = [EXEC], Defs = [EXEC] 1233 1234 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1235 1236 def SI_INDIRECT_SRC : InstSI < 1237 (outs VReg_32:$dst, SReg_64:$temp), 1238 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1239 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1240 [] 1241 >; 1242 1243 class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1244 (outs rc:$dst, SReg_64:$temp), 1245 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1246 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1247 [] 1248 > { 1249 let Constraints = "$src = $dst"; 1250 } 1251 1252 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1253 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1254 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1255 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1256 1257 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1258 1259 let usesCustomInserter = 1 in { 1260 1261 // This psuedo instruction takes a pointer as input and outputs a resource 1262 // constant that can be used with the ADDR64 MUBUF instructions. 1263 def SI_ADDR64_RSRC : InstSI < 1264 (outs SReg_128:$srsrc), 1265 (ins SReg_64:$ptr), 1266 "", [] 1267 >; 1268 1269 def V_SUB_F64 : InstSI < 1270 (outs VReg_64:$dst), 1271 (ins VReg_64:$src0, VReg_64:$src1), 1272 "V_SUB_F64 $dst, $src0, $src1", 1273 [] 1274 >; 1275 1276 } // end usesCustomInserter 1277 1278 } // end IsCodeGenOnly, isPseudo 1279 1280 def : Pat< 1281 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 1282 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) 1283 >; 1284 1285 def : Pat < 1286 (int_AMDGPU_kilp), 1287 (SI_KILL (V_MOV_B32_e32 0xbf800000)) 1288 >; 1289 1290 /* int_SI_vs_load_input */ 1291 def : Pat< 1292 (int_SI_vs_load_input v16i8:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr), 1293 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset) 1294 >; 1295 1296 /* int_SI_export */ 1297 def : Pat < 1298 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1299 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 1300 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1301 $src0, $src1, $src2, $src3) 1302 >; 1303 1304 def : Pat < 1305 (f64 (fsub f64:$src0, f64:$src1)), 1306 (V_SUB_F64 $src0, $src1) 1307 >; 1308 1309 /********** ======================= **********/ 1310 /********** Image sampling patterns **********/ 1311 /********** ======================= **********/ 1312 1313 /* int_SI_sample for simple 1D texture lookup */ 1314 def : Pat < 1315 (int_SI_sample v1i32:$addr, v32i8:$rsrc, v16i8:$sampler, imm), 1316 (IMAGE_SAMPLE 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1317 >; 1318 1319 class SamplePattern<Intrinsic name, MIMG opcode, ValueType vt> : Pat < 1320 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, imm), 1321 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1322 >; 1323 1324 class SampleRectPattern<Intrinsic name, MIMG opcode, ValueType vt> : Pat < 1325 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, TEX_RECT), 1326 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1327 >; 1328 1329 class SampleArrayPattern<Intrinsic name, MIMG opcode, ValueType vt> : Pat < 1330 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, TEX_ARRAY), 1331 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1332 >; 1333 1334 class SampleShadowPattern<Intrinsic name, MIMG opcode, 1335 ValueType vt> : Pat < 1336 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, TEX_SHADOW), 1337 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1338 >; 1339 1340 class SampleShadowArrayPattern<Intrinsic name, MIMG opcode, 1341 ValueType vt> : Pat < 1342 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, TEX_SHADOW_ARRAY), 1343 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1344 >; 1345 1346 /* int_SI_sample* for texture lookups consuming more address parameters */ 1347 multiclass SamplePatterns<ValueType addr_type> { 1348 def : SamplePattern <int_SI_sample, IMAGE_SAMPLE, addr_type>; 1349 def : SampleRectPattern <int_SI_sample, IMAGE_SAMPLE, addr_type>; 1350 def : SampleArrayPattern <int_SI_sample, IMAGE_SAMPLE, addr_type>; 1351 def : SampleShadowPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_type>; 1352 def : SampleShadowArrayPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_type>; 1353 1354 def : SamplePattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_type>; 1355 def : SampleArrayPattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_type>; 1356 def : SampleShadowPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_type>; 1357 def : SampleShadowArrayPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_type>; 1358 1359 def : SamplePattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_type>; 1360 def : SampleArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_type>; 1361 def : SampleShadowPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_type>; 1362 def : SampleShadowArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_type>; 1363 1364 def : SamplePattern <int_SI_sampled, IMAGE_SAMPLE_D, addr_type>; 1365 def : SampleArrayPattern <int_SI_sampled, IMAGE_SAMPLE_D, addr_type>; 1366 def : SampleShadowPattern <int_SI_sampled, IMAGE_SAMPLE_C_D, addr_type>; 1367 def : SampleShadowArrayPattern <int_SI_sampled, IMAGE_SAMPLE_C_D, addr_type>; 1368 } 1369 1370 defm : SamplePatterns<v2i32>; 1371 defm : SamplePatterns<v4i32>; 1372 defm : SamplePatterns<v8i32>; 1373 defm : SamplePatterns<v16i32>; 1374 1375 /* int_SI_imageload for texture fetches consuming varying address parameters */ 1376 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1377 (name addr_type:$addr, v32i8:$rsrc, imm), 1378 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1379 >; 1380 1381 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1382 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 1383 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1384 >; 1385 1386 multiclass ImageLoadPatterns<ValueType addr_type> { 1387 def : ImageLoadPattern <int_SI_imageload, IMAGE_LOAD_MIP, addr_type>; 1388 def : ImageLoadArrayPattern <int_SI_imageload, IMAGE_LOAD_MIP, addr_type>; 1389 } 1390 1391 defm : ImageLoadPatterns<v2i32>; 1392 defm : ImageLoadPatterns<v4i32>; 1393 1394 /* Image resource information */ 1395 def : Pat < 1396 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 1397 (IMAGE_GET_RESINFO 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1398 >; 1399 1400 def : Pat < 1401 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 1402 (IMAGE_GET_RESINFO 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1403 >; 1404 1405 /********** ============================================ **********/ 1406 /********** Extraction, Insertion, Building and Casting **********/ 1407 /********** ============================================ **********/ 1408 1409 foreach Index = 0-2 in { 1410 def Extract_Element_v2i32_#Index : Extract_Element < 1411 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1412 >; 1413 def Insert_Element_v2i32_#Index : Insert_Element < 1414 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1415 >; 1416 1417 def Extract_Element_v2f32_#Index : Extract_Element < 1418 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1419 >; 1420 def Insert_Element_v2f32_#Index : Insert_Element < 1421 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1422 >; 1423 } 1424 1425 foreach Index = 0-3 in { 1426 def Extract_Element_v4i32_#Index : Extract_Element < 1427 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1428 >; 1429 def Insert_Element_v4i32_#Index : Insert_Element < 1430 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1431 >; 1432 1433 def Extract_Element_v4f32_#Index : Extract_Element < 1434 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1435 >; 1436 def Insert_Element_v4f32_#Index : Insert_Element < 1437 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1438 >; 1439 } 1440 1441 foreach Index = 0-7 in { 1442 def Extract_Element_v8i32_#Index : Extract_Element < 1443 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1444 >; 1445 def Insert_Element_v8i32_#Index : Insert_Element < 1446 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1447 >; 1448 1449 def Extract_Element_v8f32_#Index : Extract_Element < 1450 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1451 >; 1452 def Insert_Element_v8f32_#Index : Insert_Element < 1453 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1454 >; 1455 } 1456 1457 foreach Index = 0-15 in { 1458 def Extract_Element_v16i32_#Index : Extract_Element < 1459 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1460 >; 1461 def Insert_Element_v16i32_#Index : Insert_Element < 1462 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1463 >; 1464 1465 def Extract_Element_v16f32_#Index : Extract_Element < 1466 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1467 >; 1468 def Insert_Element_v16f32_#Index : Insert_Element < 1469 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1470 >; 1471 } 1472 1473 def : Vector1_Build <v1i32, i32, VReg_32>; 1474 def : Vector2_Build <v2i32, i32>; 1475 def : Vector2_Build <v2f32, f32>; 1476 def : Vector4_Build <v4i32, i32>; 1477 def : Vector4_Build <v4f32, f32>; 1478 def : Vector8_Build <v8i32, i32>; 1479 def : Vector8_Build <v8f32, f32>; 1480 def : Vector16_Build <v16i32, i32>; 1481 def : Vector16_Build <v16f32, f32>; 1482 1483 def : BitConvert <i32, f32, SReg_32>; 1484 def : BitConvert <i32, f32, VReg_32>; 1485 1486 def : BitConvert <f32, i32, SReg_32>; 1487 def : BitConvert <f32, i32, VReg_32>; 1488 1489 def : BitConvert <i64, f64, VReg_64>; 1490 1491 def : BitConvert <f64, i64, VReg_64>; 1492 1493 def : BitConvert <v2f32, v2i32, VReg_64>; 1494 def : BitConvert <v2i32, v2f32, VReg_64>; 1495 1496 def : BitConvert <v4f32, v4i32, VReg_128>; 1497 def : BitConvert <v4i32, v4f32, VReg_128>; 1498 1499 /********** =================== **********/ 1500 /********** Src & Dst modifiers **********/ 1501 /********** =================== **********/ 1502 1503 def : Pat < 1504 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1505 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1506 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1507 >; 1508 1509 def : Pat < 1510 (fabs f32:$src), 1511 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1512 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1513 >; 1514 1515 def : Pat < 1516 (fneg f32:$src), 1517 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1518 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */) 1519 >; 1520 1521 /********** ================== **********/ 1522 /********** Immediate Patterns **********/ 1523 /********** ================== **********/ 1524 1525 def : Pat < 1526 (i32 imm:$imm), 1527 (V_MOV_B32_e32 imm:$imm) 1528 >; 1529 1530 def : Pat < 1531 (f32 fpimm:$imm), 1532 (V_MOV_B32_e32 fpimm:$imm) 1533 >; 1534 1535 def : Pat < 1536 (i1 imm:$imm), 1537 (S_MOV_B64 imm:$imm) 1538 >; 1539 1540 def : Pat < 1541 (i64 InlineImm<i64>:$imm), 1542 (S_MOV_B64 InlineImm<i64>:$imm) 1543 >; 1544 1545 // i64 immediates aren't supported in hardware, split it into two 32bit values 1546 def : Pat < 1547 (i64 imm:$imm), 1548 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1549 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1550 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1551 >; 1552 1553 def : Pat < 1554 (f64 fpimm:$imm), 1555 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 1556 (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0), 1557 (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1) 1558 >; 1559 1560 /********** ===================== **********/ 1561 /********** Interpolation Paterns **********/ 1562 /********** ===================== **********/ 1563 1564 def : Pat < 1565 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params), 1566 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params) 1567 >; 1568 1569 def : Pat < 1570 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij), 1571 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0), 1572 imm:$attr_chan, imm:$attr, i32:$params), 1573 (EXTRACT_SUBREG $ij, sub1), 1574 imm:$attr_chan, imm:$attr, $params) 1575 >; 1576 1577 /********** ================== **********/ 1578 /********** Intrinsic Patterns **********/ 1579 /********** ================== **********/ 1580 1581 /* llvm.AMDGPU.pow */ 1582 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 1583 1584 def : Pat < 1585 (int_AMDGPU_div f32:$src0, f32:$src1), 1586 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 1587 >; 1588 1589 def : Pat< 1590 (fdiv f32:$src0, f32:$src1), 1591 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) 1592 >; 1593 1594 def : Pat< 1595 (fdiv f64:$src0, f64:$src1), 1596 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) 1597 >; 1598 1599 def : Pat < 1600 (fcos f32:$src0), 1601 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1602 >; 1603 1604 def : Pat < 1605 (fsin f32:$src0), 1606 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1607 >; 1608 1609 def : Pat < 1610 (int_AMDGPU_cube v4f32:$src), 1611 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1612 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), 1613 (EXTRACT_SUBREG $src, sub1), 1614 (EXTRACT_SUBREG $src, sub2)), 1615 sub0), 1616 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), 1617 (EXTRACT_SUBREG $src, sub1), 1618 (EXTRACT_SUBREG $src, sub2)), 1619 sub1), 1620 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), 1621 (EXTRACT_SUBREG $src, sub1), 1622 (EXTRACT_SUBREG $src, sub2)), 1623 sub2), 1624 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), 1625 (EXTRACT_SUBREG $src, sub1), 1626 (EXTRACT_SUBREG $src, sub2)), 1627 sub3) 1628 >; 1629 1630 def : Pat < 1631 (i32 (sext i1:$src0)), 1632 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 1633 >; 1634 1635 // 1. Offset as 8bit DWORD immediate 1636 def : Pat < 1637 (int_SI_load_const v16i8:$sbase, IMM8bitDWORD:$offset), 1638 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset) 1639 >; 1640 1641 // 2. Offset loaded in an 32bit SGPR 1642 def : Pat < 1643 (int_SI_load_const v16i8:$sbase, imm:$offset), 1644 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) 1645 >; 1646 1647 // 3. Offset in an 32Bit VGPR 1648 def : Pat < 1649 (int_SI_load_const v16i8:$sbase, i32:$voff), 1650 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff) 1651 >; 1652 1653 // The multiplication scales from [0,1] to the unsigned integer range 1654 def : Pat < 1655 (AMDGPUurecip i32:$src0), 1656 (V_CVT_U32_F32_e32 1657 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 1658 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 1659 >; 1660 1661 def : Pat < 1662 (int_SI_tid), 1663 (V_MBCNT_HI_U32_B32_e32 0xffffffff, 1664 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0)) 1665 >; 1666 1667 /********** ================== **********/ 1668 /********** VOP3 Patterns **********/ 1669 /********** ================== **********/ 1670 1671 def : Pat < 1672 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)), 1673 (V_MAD_F32 $src0, $src1, $src2) 1674 >; 1675 1676 /********** ======================= **********/ 1677 /********** Load/Store Patterns **********/ 1678 /********** ======================= **********/ 1679 1680 def : Pat < 1681 (local_load i64:$src0), 1682 (i32 (DS_READ_B32 0, (EXTRACT_SUBREG $src0, sub0), 1683 (EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0)) 1684 >; 1685 1686 def : Pat < 1687 (local_store i32:$src1, i64:$src0), 1688 (DS_WRITE_B32 0, (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0) 1689 >; 1690 1691 /********** ================== **********/ 1692 /********** SMRD Patterns **********/ 1693 /********** ================== **********/ 1694 1695 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1696 1697 // 1. Offset as 8bit DWORD immediate 1698 def : Pat < 1699 (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)), 1700 (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset)) 1701 >; 1702 1703 // 2. Offset loaded in an 32bit SGPR 1704 def : Pat < 1705 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)), 1706 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset))) 1707 >; 1708 1709 // 3. No offset at all 1710 def : Pat < 1711 (constant_load i64:$sbase), 1712 (vt (Instr_IMM $sbase, 0)) 1713 >; 1714 } 1715 1716 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1717 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1718 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>; 1719 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>; 1720 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v16i8>; 1721 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1722 1723 //===----------------------------------------------------------------------===// 1724 // MUBUF Patterns 1725 //===----------------------------------------------------------------------===// 1726 1727 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 1728 PatFrag global_ld, PatFrag constant_ld> { 1729 def : Pat < 1730 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), 1731 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 1732 >; 1733 1734 def : Pat < 1735 (vt (global_ld i64:$ptr)), 1736 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1737 >; 1738 1739 def : Pat < 1740 (vt (global_ld (add i64:$ptr, i64:$offset))), 1741 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1742 >; 1743 1744 def : Pat < 1745 (vt (constant_ld (add i64:$ptr, i64:$offset))), 1746 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1747 >; 1748 } 1749 1750 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, 1751 sextloadi8_global, sextloadi8_constant>; 1752 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, 1753 az_extloadi8_global, az_extloadi8_constant>; 1754 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, 1755 sextloadi16_global, sextloadi16_constant>; 1756 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, 1757 az_extloadi16_global, az_extloadi16_constant>; 1758 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, 1759 global_load, constant_load>; 1760 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1761 global_load, constant_load>; 1762 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1763 az_extloadi32_global, az_extloadi32_constant>; 1764 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, 1765 global_load, constant_load>; 1766 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, 1767 global_load, constant_load>; 1768 1769 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt> { 1770 1771 def : Pat < 1772 (global_store vt:$value, i64:$ptr), 1773 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1774 >; 1775 1776 def : Pat < 1777 (global_store vt:$value, (add i64:$ptr, i64:$offset)), 1778 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0) 1779 >; 1780 } 1781 1782 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32>; 1783 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64>; 1784 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32>; 1785 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32>; 1786 1787 /********** ====================== **********/ 1788 /********** Indirect adressing **********/ 1789 /********** ====================== **********/ 1790 1791 multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { 1792 1793 // 1. Extract with offset 1794 def : Pat< 1795 (vector_extract vt:$vec, (add i32:$idx, imm:$off)), 1796 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) 1797 >; 1798 1799 // 2. Extract without offset 1800 def : Pat< 1801 (vector_extract vt:$vec, i32:$idx), 1802 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) 1803 >; 1804 1805 // 3. Insert with offset 1806 def : Pat< 1807 (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)), 1808 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) 1809 >; 1810 1811 // 4. Insert without offset 1812 def : Pat< 1813 (vector_insert vt:$vec, f32:$val, i32:$idx), 1814 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) 1815 >; 1816 } 1817 1818 defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>; 1819 defm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>; 1820 defm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>; 1821 defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>; 1822 1823 /********** =============== **********/ 1824 /********** Conditions **********/ 1825 /********** =============== **********/ 1826 1827 def : Pat< 1828 (i1 (setcc f32:$src0, f32:$src1, SETO)), 1829 (V_CMP_O_F32_e64 $src0, $src1) 1830 >; 1831 1832 def : Pat< 1833 (i1 (setcc f32:$src0, f32:$src1, SETUO)), 1834 (V_CMP_U_F32_e64 $src0, $src1) 1835 >; 1836 1837 //============================================================================// 1838 // Miscellaneous Optimization Patterns 1839 //============================================================================// 1840 1841 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>; 1842 1843 } // End isSI predicate 1844
