| /external/llvm/lib/Target/Mips/ |
| MipsDSPInstrInfo.td | 128 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
155 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
182 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
184 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
193 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
221 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
[all...] |
| Mips16InstrFormats.td | 419 let Inst{31-27} = 0b00011;
|
| Mips16InstrInfo.td | 1150 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrNEON.td | 302 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
306 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
310 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
351 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
356 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
386 0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
389 0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
480 0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
482 0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
487 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>
[all...] |
| /external/arduino/hardware/arduino/cores/arduino/ |
| binary.h | 30 #define B00011 3
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrFormats.td | 500 let Inst{27-23} = 0b00011;
514 let Inst{27-23} = 0b00011;
[all...] |
| ARMInstrNEON.td | [all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 574 // 0b00011: implied 0F 3A leading opcode bytes
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 850 // 0b00011: implied 0F 3A leading opcode bytes
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.td | 352 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
[all...] |
