1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips DSP ASE instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // ImmLeaf 15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>; 16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>; 17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>; 18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>; 19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>; 20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>; 21 22 // Mips-specific dsp nodes 23 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 24 SDTCisVT<2, untyped>]>; 25 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 26 SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>; 27 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 28 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 29 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 30 SDTCisVT<2, i32>]>; 31 32 class MipsDSPBase<string Opc, SDTypeProfile Prof> : 33 SDNode<!strconcat("MipsISD::", Opc), Prof>; 34 35 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> : 36 SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>; 37 38 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>; 39 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>; 40 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>; 41 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>; 42 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>; 43 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>; 44 45 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>; 46 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>; 47 48 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>; 49 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>; 50 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>; 51 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>; 52 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>; 53 54 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>; 55 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>; 56 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>; 57 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>; 58 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>; 59 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>; 60 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>; 61 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>; 62 63 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>; 64 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>; 65 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>; 66 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>; 67 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>; 68 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>; 69 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>; 70 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>; 71 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>; 72 73 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>; 74 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>; 75 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>; 76 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>; 77 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>; 78 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>; 79 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>; 80 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>; 81 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>; 82 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>; 83 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>; 84 85 // Flags. 86 class Uses<list<Register> Regs> { 87 list<Register> Uses = Regs; 88 } 89 90 class Defs<list<Register> Regs> { 91 list<Register> Defs = Regs; 92 } 93 94 // Instruction encoding. 95 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>; 96 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>; 97 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>; 98 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>; 99 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>; 100 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>; 101 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>; 102 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>; 103 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>; 104 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>; 105 class ADDSC_ENC : ADDU_QB_FMT<0b10000>; 106 class ADDWC_ENC : ADDU_QB_FMT<0b10001>; 107 class MODSUB_ENC : ADDU_QB_FMT<0b10010>; 108 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>; 109 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>; 110 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>; 111 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>; 112 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>; 113 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>; 114 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>; 115 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>; 116 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>; 117 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>; 118 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>; 119 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>; 120 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>; 121 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>; 122 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>; 123 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>; 124 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>; 125 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>; 126 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>; 127 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>; 128 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>; 129 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>; 130 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>; 131 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>; 132 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>; 133 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>; 134 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>; 135 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>; 136 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>; 137 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>; 138 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>; 139 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>; 140 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>; 141 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>; 142 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>; 143 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>; 144 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>; 145 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>; 146 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>; 147 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>; 148 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>; 149 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>; 150 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>; 151 class MFHI_ENC : MFHI_FMT<0b010000>; 152 class MFLO_ENC : MFHI_FMT<0b010010>; 153 class MTHI_ENC : MTHI_FMT<0b010001>; 154 class MTLO_ENC : MTHI_FMT<0b010011>; 155 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>; 156 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>; 157 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>; 158 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>; 159 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>; 160 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>; 161 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>; 162 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>; 163 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>; 164 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>; 165 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>; 166 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>; 167 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>; 168 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>; 169 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>; 170 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>; 171 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>; 172 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>; 173 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>; 174 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>; 175 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>; 176 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>; 177 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>; 178 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>; 179 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>; 180 class REPL_QB_ENC : REPL_FMT<0b00010>; 181 class REPL_PH_ENC : REPL_FMT<0b01010>; 182 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>; 183 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>; 184 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>; 185 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>; 186 class LWX_ENC : LX_FMT<0b00000>; 187 class LHX_ENC : LX_FMT<0b00100>; 188 class LBUX_ENC : LX_FMT<0b00110>; 189 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>; 190 class INSV_ENC : INSV_FMT<0b001100>; 191 192 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>; 193 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>; 194 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>; 195 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>; 196 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>; 197 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>; 198 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>; 199 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>; 200 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>; 201 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>; 202 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>; 203 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>; 204 class SHILO_ENC : SHILO_R1_FMT<0b11010>; 205 class SHILOV_ENC : SHILO_R2_FMT<0b11011>; 206 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>; 207 208 class RDDSP_ENC : RDDSP_FMT<0b10010>; 209 class WRDSP_ENC : WRDSP_FMT<0b10011>; 210 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>; 211 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>; 212 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>; 213 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>; 214 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>; 215 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>; 216 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>; 217 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>; 218 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>; 219 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>; 220 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>; 221 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>; 222 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>; 223 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>; 224 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>; 225 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>; 226 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>; 227 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>; 228 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>; 229 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>; 230 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>; 231 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>; 232 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>; 233 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>; 234 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>; 235 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>; 236 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>; 237 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>; 238 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>; 239 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>; 240 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>; 241 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>; 242 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>; 243 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>; 244 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>; 245 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>; 246 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>; 247 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>; 248 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>; 249 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>; 250 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>; 251 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>; 252 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>; 253 class APPEND_ENC : APPEND_FMT<0b00000>; 254 class BALIGN_ENC : APPEND_FMT<0b10000>; 255 class PREPEND_ENC : APPEND_FMT<0b00001>; 256 257 // Instruction desc. 258 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 259 InstrItinClass itin, RegisterClass RCD, 260 RegisterClass RCS, RegisterClass RCT = RCS> { 261 dag OutOperandList = (outs RCD:$rd); 262 dag InOperandList = (ins RCS:$rs, RCT:$rt); 263 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 264 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 265 InstrItinClass Itinerary = itin; 266 } 267 268 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 269 InstrItinClass itin, RegisterClass RCD, 270 RegisterClass RCS = RCD> { 271 dag OutOperandList = (outs RCD:$rd); 272 dag InOperandList = (ins RCS:$rs); 273 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 274 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))]; 275 InstrItinClass Itinerary = itin; 276 } 277 278 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 279 InstrItinClass itin, RegisterClass RCS, 280 RegisterClass RCT = RCS> { 281 dag OutOperandList = (outs); 282 dag InOperandList = (ins RCS:$rs, RCT:$rt); 283 string AsmString = !strconcat(instr_asm, "\t$rs, $rt"); 284 list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)]; 285 InstrItinClass Itinerary = itin; 286 } 287 288 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 289 InstrItinClass itin, RegisterClass RCD, 290 RegisterClass RCS, RegisterClass RCT = RCS> { 291 dag OutOperandList = (outs RCD:$rd); 292 dag InOperandList = (ins RCS:$rs, RCT:$rt); 293 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 294 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 295 InstrItinClass Itinerary = itin; 296 } 297 298 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 299 InstrItinClass itin, RegisterClass RCT, 300 RegisterClass RCS = RCT> { 301 dag OutOperandList = (outs RCT:$rt); 302 dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src); 303 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 304 list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))]; 305 InstrItinClass Itinerary = itin; 306 string Constraints = "$src = $rt"; 307 } 308 309 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 310 InstrItinClass itin, RegisterClass RCD, 311 RegisterClass RCT = RCD> { 312 dag OutOperandList = (outs RCD:$rd); 313 dag InOperandList = (ins RCT:$rt); 314 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 315 list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))]; 316 InstrItinClass Itinerary = itin; 317 } 318 319 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 320 ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> { 321 dag OutOperandList = (outs RC:$rd); 322 dag InOperandList = (ins uimm16:$imm); 323 string AsmString = !strconcat(instr_asm, "\t$rd, $imm"); 324 list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))]; 325 InstrItinClass Itinerary = itin; 326 } 327 328 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 329 InstrItinClass itin, RegisterClass RC> { 330 dag OutOperandList = (outs RC:$rd); 331 dag InOperandList = (ins RC:$rt, GPR32:$rs_sa); 332 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 333 list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, GPR32:$rs_sa))]; 334 InstrItinClass Itinerary = itin; 335 } 336 337 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 338 SDPatternOperator ImmPat, InstrItinClass itin, 339 RegisterClass RC> { 340 dag OutOperandList = (outs RC:$rd); 341 dag InOperandList = (ins RC:$rt, uimm16:$rs_sa); 342 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 343 list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))]; 344 InstrItinClass Itinerary = itin; 345 bit hasSideEffects = 1; 346 } 347 348 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 349 InstrItinClass itin> { 350 dag OutOperandList = (outs GPR32:$rd); 351 dag InOperandList = (ins GPR32:$base, GPR32:$index); 352 string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})"); 353 list<dag> Pattern = [(set GPR32:$rd, 354 (OpNode GPR32:$base, GPR32:$index))]; 355 InstrItinClass Itinerary = itin; 356 bit mayLoad = 1; 357 } 358 359 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 360 InstrItinClass itin, RegisterClass RCD, 361 RegisterClass RCS = RCD, RegisterClass RCT = RCD> { 362 dag OutOperandList = (outs RCD:$rd); 363 dag InOperandList = (ins RCS:$rs, RCT:$rt); 364 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 365 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 366 InstrItinClass Itinerary = itin; 367 } 368 369 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 370 SDPatternOperator ImmOp, InstrItinClass itin> { 371 dag OutOperandList = (outs GPR32:$rt); 372 dag InOperandList = (ins GPR32:$rs, shamt:$sa, GPR32:$src); 373 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 374 list<dag> Pattern = [(set GPR32:$rt, 375 (OpNode GPR32:$src, GPR32:$rs, ImmOp:$sa))]; 376 InstrItinClass Itinerary = itin; 377 string Constraints = "$src = $rt"; 378 } 379 380 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 381 InstrItinClass itin> { 382 dag OutOperandList = (outs GPR32:$rt); 383 dag InOperandList = (ins ACRegsDSP:$ac, GPR32:$shift_rs); 384 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 385 InstrItinClass Itinerary = itin; 386 } 387 388 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 389 InstrItinClass itin> { 390 dag OutOperandList = (outs GPR32:$rt); 391 dag InOperandList = (ins ACRegsDSP:$ac, uimm16:$shift_rs); 392 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 393 InstrItinClass Itinerary = itin; 394 } 395 396 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 397 dag OutOperandList = (outs ACRegsDSP:$ac); 398 dag InOperandList = (ins simm16:$shift, ACRegsDSP:$acin); 399 string AsmString = !strconcat(instr_asm, "\t$ac, $shift"); 400 list<dag> Pattern = [(set ACRegsDSP:$ac, 401 (OpNode immSExt6:$shift, ACRegsDSP:$acin))]; 402 string Constraints = "$acin = $ac"; 403 } 404 405 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 406 dag OutOperandList = (outs ACRegsDSP:$ac); 407 dag InOperandList = (ins GPR32:$rs, ACRegsDSP:$acin); 408 string AsmString = !strconcat(instr_asm, "\t$ac, $rs"); 409 list<dag> Pattern = [(set ACRegsDSP:$ac, 410 (OpNode GPR32:$rs, ACRegsDSP:$acin))]; 411 string Constraints = "$acin = $ac"; 412 } 413 414 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 415 dag OutOperandList = (outs ACRegsDSP:$ac); 416 dag InOperandList = (ins GPR32:$rs, ACRegsDSP:$acin); 417 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 418 list<dag> Pattern = [(set ACRegsDSP:$ac, 419 (OpNode GPR32:$rs, ACRegsDSP:$acin))]; 420 string Constraints = "$acin = $ac"; 421 } 422 423 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 424 InstrItinClass itin> { 425 dag OutOperandList = (outs GPR32:$rd); 426 dag InOperandList = (ins uimm16:$mask); 427 string AsmString = !strconcat(instr_asm, "\t$rd, $mask"); 428 list<dag> Pattern = [(set GPR32:$rd, (OpNode immZExt10:$mask))]; 429 InstrItinClass Itinerary = itin; 430 } 431 432 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 433 InstrItinClass itin> { 434 dag OutOperandList = (outs); 435 dag InOperandList = (ins GPR32:$rs, uimm16:$mask); 436 string AsmString = !strconcat(instr_asm, "\t$rs, $mask"); 437 list<dag> Pattern = [(OpNode GPR32:$rs, immZExt10:$mask)]; 438 InstrItinClass Itinerary = itin; 439 } 440 441 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 442 dag OutOperandList = (outs ACRegsDSP:$ac); 443 dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin); 444 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 445 list<dag> Pattern = [(set ACRegsDSP:$ac, 446 (OpNode GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin))]; 447 string Constraints = "$acin = $ac"; 448 } 449 450 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 451 InstrItinClass itin> { 452 dag OutOperandList = (outs ACRegsDSP:$ac); 453 dag InOperandList = (ins GPR32:$rs, GPR32:$rt); 454 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 455 list<dag> Pattern = [(set ACRegsDSP:$ac, (OpNode GPR32:$rs, GPR32:$rt))]; 456 InstrItinClass Itinerary = itin; 457 int AddedComplexity = 20; 458 bit isCommutable = 1; 459 } 460 461 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 462 InstrItinClass itin> { 463 dag OutOperandList = (outs ACRegsDSP:$ac); 464 dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin); 465 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 466 list<dag> Pattern = [(set ACRegsDSP:$ac, 467 (OpNode GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin))]; 468 InstrItinClass Itinerary = itin; 469 int AddedComplexity = 20; 470 string Constraints = "$acin = $ac"; 471 } 472 473 class MFHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> { 474 dag OutOperandList = (outs GPR32:$rd); 475 dag InOperandList = (ins RC:$ac); 476 string AsmString = !strconcat(instr_asm, "\t$rd, $ac"); 477 InstrItinClass Itinerary = itin; 478 } 479 480 class MTHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> { 481 dag OutOperandList = (outs RC:$ac); 482 dag InOperandList = (ins GPR32:$rs); 483 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 484 InstrItinClass Itinerary = itin; 485 } 486 487 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> : 488 MipsPseudo<(outs GPR32:$dst), (ins), [(set GPR32:$dst, (OpNode))]> { 489 bit usesCustomInserter = 1; 490 } 491 492 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> { 493 dag OutOperandList = (outs); 494 dag InOperandList = (ins brtarget:$offset); 495 string AsmString = !strconcat(instr_asm, "\t$offset"); 496 InstrItinClass Itinerary = itin; 497 bit isBranch = 1; 498 bit isTerminator = 1; 499 bit hasDelaySlot = 1; 500 } 501 502 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 503 InstrItinClass itin> { 504 dag OutOperandList = (outs GPR32:$rt); 505 dag InOperandList = (ins GPR32:$src, GPR32:$rs); 506 string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); 507 list<dag> Pattern = [(set GPR32:$rt, (OpNode GPR32:$src, GPR32:$rs))]; 508 InstrItinClass Itinerary = itin; 509 string Constraints = "$src = $rt"; 510 } 511 512 //===----------------------------------------------------------------------===// 513 // MIPS DSP Rev 1 514 //===----------------------------------------------------------------------===// 515 516 // Addition/subtraction 517 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary, 518 DSPRegs, DSPRegs>, IsCommutable, 519 Defs<[DSPOutFlag20]>; 520 521 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb, 522 NoItinerary, DSPRegs, DSPRegs>, 523 IsCommutable, Defs<[DSPOutFlag20]>; 524 525 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary, 526 DSPRegs, DSPRegs>, 527 Defs<[DSPOutFlag20]>; 528 529 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb, 530 NoItinerary, DSPRegs, DSPRegs>, 531 Defs<[DSPOutFlag20]>; 532 533 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary, 534 DSPRegs, DSPRegs>, IsCommutable, 535 Defs<[DSPOutFlag20]>; 536 537 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph, 538 NoItinerary, DSPRegs, DSPRegs>, 539 IsCommutable, Defs<[DSPOutFlag20]>; 540 541 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary, 542 DSPRegs, DSPRegs>, 543 Defs<[DSPOutFlag20]>; 544 545 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph, 546 NoItinerary, DSPRegs, DSPRegs>, 547 Defs<[DSPOutFlag20]>; 548 549 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w, 550 NoItinerary, GPR32, GPR32>, 551 IsCommutable, Defs<[DSPOutFlag20]>; 552 553 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w, 554 NoItinerary, GPR32, GPR32>, 555 Defs<[DSPOutFlag20]>; 556 557 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary, 558 GPR32, GPR32>, IsCommutable, 559 Defs<[DSPCarry]>; 560 561 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary, 562 GPR32, GPR32>, 563 IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>; 564 565 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary, 566 GPR32, GPR32>; 567 568 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb, 569 NoItinerary, GPR32, DSPRegs>; 570 571 // Absolute value 572 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph, 573 NoItinerary, DSPRegs>, 574 Defs<[DSPOutFlag20]>; 575 576 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w, 577 NoItinerary, GPR32>, 578 Defs<[DSPOutFlag20]>; 579 580 // Precision reduce/expand 581 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph", 582 int_mips_precrq_qb_ph, 583 NoItinerary, DSPRegs, DSPRegs>; 584 585 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w", 586 int_mips_precrq_ph_w, 587 NoItinerary, DSPRegs, GPR32>; 588 589 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w", 590 int_mips_precrq_rs_ph_w, 591 NoItinerary, DSPRegs, 592 GPR32>, 593 Defs<[DSPOutFlag22]>; 594 595 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph", 596 int_mips_precrqu_s_qb_ph, 597 NoItinerary, DSPRegs, 598 DSPRegs>, 599 Defs<[DSPOutFlag22]>; 600 601 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl", 602 int_mips_preceq_w_phl, 603 NoItinerary, GPR32, DSPRegs>; 604 605 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr", 606 int_mips_preceq_w_phr, 607 NoItinerary, GPR32, DSPRegs>; 608 609 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl", 610 int_mips_precequ_ph_qbl, 611 NoItinerary, DSPRegs>; 612 613 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr", 614 int_mips_precequ_ph_qbr, 615 NoItinerary, DSPRegs>; 616 617 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla", 618 int_mips_precequ_ph_qbla, 619 NoItinerary, DSPRegs>; 620 621 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra", 622 int_mips_precequ_ph_qbra, 623 NoItinerary, DSPRegs>; 624 625 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl", 626 int_mips_preceu_ph_qbl, 627 NoItinerary, DSPRegs>; 628 629 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr", 630 int_mips_preceu_ph_qbr, 631 NoItinerary, DSPRegs>; 632 633 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla", 634 int_mips_preceu_ph_qbla, 635 NoItinerary, DSPRegs>; 636 637 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra", 638 int_mips_preceu_ph_qbra, 639 NoItinerary, DSPRegs>; 640 641 // Shift 642 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3, 643 NoItinerary, DSPRegs>, 644 Defs<[DSPOutFlag22]>; 645 646 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb, 647 NoItinerary, DSPRegs>, 648 Defs<[DSPOutFlag22]>; 649 650 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3, 651 NoItinerary, DSPRegs>; 652 653 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb, 654 NoItinerary, DSPRegs>; 655 656 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4, 657 NoItinerary, DSPRegs>, 658 Defs<[DSPOutFlag22]>; 659 660 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph, 661 NoItinerary, DSPRegs>, 662 Defs<[DSPOutFlag22]>; 663 664 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph, 665 immZExt4, NoItinerary, DSPRegs>, 666 Defs<[DSPOutFlag22]>; 667 668 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph, 669 NoItinerary, DSPRegs>, 670 Defs<[DSPOutFlag22]>; 671 672 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4, 673 NoItinerary, DSPRegs>; 674 675 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph, 676 NoItinerary, DSPRegs>; 677 678 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph, 679 immZExt4, NoItinerary, DSPRegs>; 680 681 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph, 682 NoItinerary, DSPRegs>; 683 684 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w, 685 immZExt5, NoItinerary, GPR32>, 686 Defs<[DSPOutFlag22]>; 687 688 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w, 689 NoItinerary, GPR32>, 690 Defs<[DSPOutFlag22]>; 691 692 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w, 693 immZExt5, NoItinerary, GPR32>; 694 695 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w, 696 NoItinerary, GPR32>; 697 698 // Multiplication 699 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl", 700 int_mips_muleu_s_ph_qbl, 701 NoItinerary, DSPRegs, DSPRegs>, 702 Defs<[DSPOutFlag21]>; 703 704 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr", 705 int_mips_muleu_s_ph_qbr, 706 NoItinerary, DSPRegs, DSPRegs>, 707 Defs<[DSPOutFlag21]>; 708 709 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl", 710 int_mips_muleq_s_w_phl, 711 NoItinerary, GPR32, DSPRegs>, 712 IsCommutable, Defs<[DSPOutFlag21]>; 713 714 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr", 715 int_mips_muleq_s_w_phr, 716 NoItinerary, GPR32, DSPRegs>, 717 IsCommutable, Defs<[DSPOutFlag21]>; 718 719 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph, 720 NoItinerary, DSPRegs, DSPRegs>, 721 IsCommutable, Defs<[DSPOutFlag21]>; 722 723 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph", 724 MipsMULSAQ_S_W_PH>, 725 Defs<[DSPOutFlag16_19]>; 726 727 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>, 728 Defs<[DSPOutFlag16_19]>; 729 730 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>, 731 Defs<[DSPOutFlag16_19]>; 732 733 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>, 734 Defs<[DSPOutFlag16_19]>; 735 736 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>, 737 Defs<[DSPOutFlag16_19]>; 738 739 // Move from/to hi/lo. 740 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", HIRegsDSP, NoItinerary>; 741 class MFLO_DESC : MFHI_DESC_BASE<"mflo", LORegsDSP, NoItinerary>; 742 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HIRegsDSP, NoItinerary>; 743 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LORegsDSP, NoItinerary>; 744 745 // Dot product with accumulate/subtract 746 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>; 747 748 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>; 749 750 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>; 751 752 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>; 753 754 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>, 755 Defs<[DSPOutFlag16_19]>; 756 757 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>, 758 Defs<[DSPOutFlag16_19]>; 759 760 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>, 761 Defs<[DSPOutFlag16_19]>; 762 763 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>, 764 Defs<[DSPOutFlag16_19]>; 765 766 class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>; 767 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>; 768 class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>; 769 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>; 770 class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>; 771 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>; 772 773 // Comparison 774 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb", 775 int_mips_cmpu_eq_qb, NoItinerary, 776 DSPRegs>, 777 IsCommutable, Defs<[DSPCCond]>; 778 779 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb", 780 int_mips_cmpu_lt_qb, NoItinerary, 781 DSPRegs>, Defs<[DSPCCond]>; 782 783 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb", 784 int_mips_cmpu_le_qb, NoItinerary, 785 DSPRegs>, Defs<[DSPCCond]>; 786 787 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb", 788 int_mips_cmpgu_eq_qb, 789 NoItinerary, GPR32, DSPRegs>, 790 IsCommutable; 791 792 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb", 793 int_mips_cmpgu_lt_qb, 794 NoItinerary, GPR32, DSPRegs>; 795 796 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb", 797 int_mips_cmpgu_le_qb, 798 NoItinerary, GPR32, DSPRegs>; 799 800 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph, 801 NoItinerary, DSPRegs>, 802 IsCommutable, Defs<[DSPCCond]>; 803 804 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph, 805 NoItinerary, DSPRegs>, 806 Defs<[DSPCCond]>; 807 808 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph, 809 NoItinerary, DSPRegs>, 810 Defs<[DSPCCond]>; 811 812 // Misc 813 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev, 814 NoItinerary, GPR32>; 815 816 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph, 817 NoItinerary, DSPRegs, DSPRegs>; 818 819 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8, 820 NoItinerary, DSPRegs>; 821 822 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10, 823 NoItinerary, DSPRegs>; 824 825 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, 826 NoItinerary, DSPRegs, GPR32>; 827 828 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph, 829 NoItinerary, DSPRegs, GPR32>; 830 831 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb, 832 NoItinerary, DSPRegs, DSPRegs>, 833 Uses<[DSPCCond]>; 834 835 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph, 836 NoItinerary, DSPRegs, DSPRegs>, 837 Uses<[DSPCCond]>; 838 839 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>; 840 841 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>; 842 843 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>; 844 845 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>; 846 847 // Extr 848 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>, 849 Uses<[DSPPos]>, Defs<[DSPEFI]>; 850 851 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>, 852 Uses<[DSPPos]>, Defs<[DSPEFI]>; 853 854 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>, 855 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>; 856 857 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP, 858 NoItinerary>, 859 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>; 860 861 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>, 862 Defs<[DSPOutFlag23]>; 863 864 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W, 865 NoItinerary>, Defs<[DSPOutFlag23]>; 866 867 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W, 868 NoItinerary>, 869 Defs<[DSPOutFlag23]>; 870 871 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, 872 NoItinerary>, 873 Defs<[DSPOutFlag23]>; 874 875 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, 876 NoItinerary>, 877 Defs<[DSPOutFlag23]>; 878 879 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, 880 NoItinerary>, 881 Defs<[DSPOutFlag23]>; 882 883 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H, 884 NoItinerary>, 885 Defs<[DSPOutFlag23]>; 886 887 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, 888 NoItinerary>, 889 Defs<[DSPOutFlag23]>; 890 891 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>; 892 893 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>; 894 895 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>; 896 897 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>; 898 899 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>; 900 901 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>, 902 Uses<[DSPPos, DSPSCount]>; 903 904 //===----------------------------------------------------------------------===// 905 // MIPS DSP Rev 2 906 // Addition/subtraction 907 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary, 908 DSPRegs, DSPRegs>, IsCommutable, 909 Defs<[DSPOutFlag20]>; 910 911 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph, 912 NoItinerary, DSPRegs, DSPRegs>, 913 IsCommutable, Defs<[DSPOutFlag20]>; 914 915 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary, 916 DSPRegs, DSPRegs>, 917 Defs<[DSPOutFlag20]>; 918 919 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph, 920 NoItinerary, DSPRegs, DSPRegs>, 921 Defs<[DSPOutFlag20]>; 922 923 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb, 924 NoItinerary, DSPRegs>, IsCommutable; 925 926 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb, 927 NoItinerary, DSPRegs>, IsCommutable; 928 929 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb, 930 NoItinerary, DSPRegs>; 931 932 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb, 933 NoItinerary, DSPRegs>; 934 935 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph, 936 NoItinerary, DSPRegs>, IsCommutable; 937 938 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph, 939 NoItinerary, DSPRegs>, IsCommutable; 940 941 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph, 942 NoItinerary, DSPRegs>; 943 944 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph, 945 NoItinerary, DSPRegs>; 946 947 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w, 948 NoItinerary, GPR32>, IsCommutable; 949 950 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w, 951 NoItinerary, GPR32>, IsCommutable; 952 953 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w, 954 NoItinerary, GPR32>; 955 956 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w, 957 NoItinerary, GPR32>; 958 959 // Comparison 960 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb", 961 int_mips_cmpgdu_eq_qb, 962 NoItinerary, GPR32, DSPRegs>, 963 IsCommutable, Defs<[DSPCCond]>; 964 965 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb", 966 int_mips_cmpgdu_lt_qb, 967 NoItinerary, GPR32, DSPRegs>, 968 Defs<[DSPCCond]>; 969 970 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb", 971 int_mips_cmpgdu_le_qb, 972 NoItinerary, GPR32, DSPRegs>, 973 Defs<[DSPCCond]>; 974 975 // Absolute 976 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb, 977 NoItinerary, DSPRegs>, 978 Defs<[DSPOutFlag20]>; 979 980 // Multiplication 981 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary, 982 DSPRegs>, IsCommutable, 983 Defs<[DSPOutFlag21]>; 984 985 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph, 986 NoItinerary, DSPRegs>, IsCommutable, 987 Defs<[DSPOutFlag21]>; 988 989 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w, 990 NoItinerary, GPR32>, IsCommutable, 991 Defs<[DSPOutFlag21]>; 992 993 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w, 994 NoItinerary, GPR32>, IsCommutable, 995 Defs<[DSPOutFlag21]>; 996 997 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph, 998 NoItinerary, DSPRegs, DSPRegs>, 999 IsCommutable, Defs<[DSPOutFlag21]>; 1000 1001 // Dot product with accumulate/subtract 1002 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>; 1003 1004 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>; 1005 1006 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>, 1007 Defs<[DSPOutFlag16_19]>; 1008 1009 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph", 1010 MipsDPAQX_SA_W_PH>, 1011 Defs<[DSPOutFlag16_19]>; 1012 1013 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>; 1014 1015 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>; 1016 1017 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>, 1018 Defs<[DSPOutFlag16_19]>; 1019 1020 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph", 1021 MipsDPSQX_SA_W_PH>, 1022 Defs<[DSPOutFlag16_19]>; 1023 1024 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>; 1025 1026 // Precision reduce/expand 1027 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph", 1028 int_mips_precr_qb_ph, 1029 NoItinerary, DSPRegs, DSPRegs>; 1030 1031 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w", 1032 int_mips_precr_sra_ph_w, 1033 NoItinerary, DSPRegs, 1034 GPR32>; 1035 1036 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w", 1037 int_mips_precr_sra_r_ph_w, 1038 NoItinerary, DSPRegs, 1039 GPR32>; 1040 1041 // Shift 1042 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3, 1043 NoItinerary, DSPRegs>; 1044 1045 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb, 1046 NoItinerary, DSPRegs>; 1047 1048 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb, 1049 immZExt3, NoItinerary, DSPRegs>; 1050 1051 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb, 1052 NoItinerary, DSPRegs>; 1053 1054 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4, 1055 NoItinerary, DSPRegs>; 1056 1057 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph, 1058 NoItinerary, DSPRegs>; 1059 1060 // Misc 1061 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5, 1062 NoItinerary>; 1063 1064 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2, 1065 NoItinerary>; 1066 1067 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5, 1068 NoItinerary>; 1069 1070 // Pseudos. 1071 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, 1072 NoItinerary>, Uses<[DSPPos]>; 1073 1074 // Instruction defs. 1075 // MIPS DSP Rev 1 1076 def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC; 1077 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC; 1078 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC; 1079 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC; 1080 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC; 1081 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC; 1082 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC; 1083 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC; 1084 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC; 1085 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC; 1086 def ADDSC : ADDSC_ENC, ADDSC_DESC; 1087 def ADDWC : ADDWC_ENC, ADDWC_DESC; 1088 def MODSUB : MODSUB_ENC, MODSUB_DESC; 1089 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC; 1090 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC; 1091 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC; 1092 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; 1093 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; 1094 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC; 1095 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC; 1096 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC; 1097 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC; 1098 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC; 1099 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC; 1100 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC; 1101 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC; 1102 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC; 1103 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC; 1104 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC; 1105 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC; 1106 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC; 1107 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC; 1108 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC; 1109 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC; 1110 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC; 1111 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC; 1112 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC; 1113 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC; 1114 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC; 1115 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC; 1116 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC; 1117 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC; 1118 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC; 1119 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC; 1120 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC; 1121 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC; 1122 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC; 1123 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC; 1124 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; 1125 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; 1126 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; 1127 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC; 1128 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; 1129 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; 1130 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC; 1131 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC; 1132 def MFHI_DSP : MFHI_ENC, MFHI_DESC; 1133 def MFLO_DSP : MFLO_ENC, MFLO_DESC; 1134 def MTHI_DSP : MTHI_ENC, MTHI_DESC; 1135 def MTLO_DSP : MTLO_ENC, MTLO_DESC; 1136 def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC; 1137 def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC; 1138 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; 1139 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC; 1140 def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC; 1141 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC; 1142 def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC; 1143 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC; 1144 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC; 1145 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC; 1146 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC; 1147 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC; 1148 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC; 1149 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC; 1150 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC; 1151 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC; 1152 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC; 1153 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC; 1154 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC; 1155 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC; 1156 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC; 1157 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC; 1158 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC; 1159 def BITREV : BITREV_ENC, BITREV_DESC; 1160 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC; 1161 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC; 1162 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC; 1163 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC; 1164 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC; 1165 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC; 1166 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC; 1167 def LWX : LWX_ENC, LWX_DESC; 1168 def LHX : LHX_ENC, LHX_DESC; 1169 def LBUX : LBUX_ENC, LBUX_DESC; 1170 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC; 1171 def INSV : INSV_ENC, INSV_DESC; 1172 def EXTP : EXTP_ENC, EXTP_DESC; 1173 def EXTPV : EXTPV_ENC, EXTPV_DESC; 1174 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC; 1175 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC; 1176 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC; 1177 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC; 1178 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC; 1179 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC; 1180 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC; 1181 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC; 1182 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC; 1183 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC; 1184 def SHILO : SHILO_ENC, SHILO_DESC; 1185 def SHILOV : SHILOV_ENC, SHILOV_DESC; 1186 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC; 1187 def RDDSP : RDDSP_ENC, RDDSP_DESC; 1188 def WRDSP : WRDSP_ENC, WRDSP_DESC; 1189 1190 // MIPS DSP Rev 2 1191 let Predicates = [HasDSPR2] in { 1192 1193 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC; 1194 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC; 1195 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC; 1196 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC; 1197 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC; 1198 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC; 1199 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC; 1200 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC; 1201 def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC; 1202 def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC; 1203 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC; 1204 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC; 1205 def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC; 1206 def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC; 1207 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC; 1208 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC; 1209 def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC; 1210 def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC; 1211 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC; 1212 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC; 1213 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC; 1214 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC; 1215 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC; 1216 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC; 1217 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC; 1218 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC; 1219 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; 1220 def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; 1221 def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC; 1222 def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC; 1223 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC; 1224 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; 1225 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; 1226 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC; 1227 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC; 1228 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC; 1229 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC; 1230 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC; 1231 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC; 1232 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC; 1233 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC; 1234 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC; 1235 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC; 1236 def APPEND : APPEND_ENC, APPEND_DESC; 1237 def BALIGN : BALIGN_ENC, BALIGN_DESC; 1238 def PREPEND : PREPEND_ENC, PREPEND_DESC; 1239 1240 } 1241 1242 // Pseudos. 1243 let isPseudo = 1 in { 1244 // Pseudo instructions for loading and storing accumulator registers. 1245 defm LOAD_AC_DSP : LoadM<"load_ac_dsp", ACRegsDSPOpnd>; 1246 defm STORE_AC_DSP : StoreM<"store_ac_dsp", ACRegsDSPOpnd>; 1247 1248 // Pseudos for loading and storing ccond field of DSP control register. 1249 defm LOAD_CCOND_DSP : LoadM<"load_ccond_dsp", DSPCC>; 1250 defm STORE_CCOND_DSP : StoreM<"store_ccond_dsp", DSPCC>; 1251 } 1252 1253 // Pseudo CMP and PICK instructions. 1254 class PseudoCMP<Instruction RealInst> : 1255 PseudoDSP<(outs DSPCC:$cmp), (ins DSPRegs:$rs, DSPRegs:$rt), []>, 1256 PseudoInstExpansion<(RealInst DSPRegs:$rs, DSPRegs:$rt)>, NeverHasSideEffects; 1257 1258 class PseudoPICK<Instruction RealInst> : 1259 PseudoDSP<(outs DSPRegs:$rd), (ins DSPCC:$cmp, DSPRegs:$rs, DSPRegs:$rt), []>, 1260 PseudoInstExpansion<(RealInst DSPRegs:$rd, DSPRegs:$rs, DSPRegs:$rt)>, 1261 NeverHasSideEffects; 1262 1263 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>; 1264 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>; 1265 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>; 1266 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>; 1267 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>; 1268 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>; 1269 1270 def PseudoPICK_PH : PseudoPICK<PICK_PH>; 1271 def PseudoPICK_QB : PseudoPICK<PICK_QB>; 1272 1273 // Patterns. 1274 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : 1275 Pat<pattern, result>, Requires<[pred]>; 1276 1277 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, 1278 RegisterClass SrcRC> : 1279 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))), 1280 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>; 1281 1282 def : BitconvertPat<i32, v2i16, GPR32, DSPRegs>; 1283 def : BitconvertPat<i32, v4i8, GPR32, DSPRegs>; 1284 def : BitconvertPat<v2i16, i32, DSPRegs, GPR32>; 1285 def : BitconvertPat<v4i8, i32, DSPRegs, GPR32>; 1286 1287 def : DSPPat<(v2i16 (load addr:$a)), 1288 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 1289 def : DSPPat<(v4i8 (load addr:$a)), 1290 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 1291 def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a), 1292 (SW (COPY_TO_REGCLASS DSPRegs:$val, GPR32), addr:$a)>; 1293 def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a), 1294 (SW (COPY_TO_REGCLASS DSPRegs:$val, GPR32), addr:$a)>; 1295 1296 // Binary operations. 1297 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node, 1298 Predicate Pred = HasDSP> : 1299 DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>; 1300 1301 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>; 1302 def : DSPBinPat<ADDQ_PH, v2i16, add>; 1303 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>; 1304 def : DSPBinPat<SUBQ_PH, v2i16, sub>; 1305 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>; 1306 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>; 1307 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>; 1308 def : DSPBinPat<ADDU_QB, v4i8, add>; 1309 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>; 1310 def : DSPBinPat<SUBU_QB, v4i8, sub>; 1311 def : DSPBinPat<ADDSC, i32, int_mips_addsc>; 1312 def : DSPBinPat<ADDSC, i32, addc>; 1313 def : DSPBinPat<ADDWC, i32, int_mips_addwc>; 1314 def : DSPBinPat<ADDWC, i32, adde>; 1315 1316 // Shift immediate patterns. 1317 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node, 1318 SDPatternOperator Imm, Predicate Pred = HasDSP> : 1319 DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>; 1320 1321 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>; 1322 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>; 1323 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>; 1324 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>; 1325 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>; 1326 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>; 1327 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>; 1328 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>; 1329 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>; 1330 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>; 1331 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>; 1332 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>; 1333 1334 // SETCC/SELECT_CC patterns. 1335 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy, 1336 CondCode CC> : 1337 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)), 1338 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), 1339 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPRegs)), 1340 (ValTy ZERO)))>; 1341 1342 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy, 1343 CondCode CC> : 1344 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)), 1345 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), 1346 (ValTy ZERO), 1347 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPRegs))))>; 1348 1349 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy, 1350 CondCode CC> : 1351 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)), 1352 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>; 1353 1354 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy, 1355 CondCode CC> : 1356 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)), 1357 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>; 1358 1359 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>; 1360 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>; 1361 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>; 1362 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>; 1363 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>; 1364 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>; 1365 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>; 1366 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>; 1367 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>; 1368 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>; 1369 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>; 1370 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>; 1371 1372 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>; 1373 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>; 1374 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>; 1375 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>; 1376 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>; 1377 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>; 1378 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>; 1379 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>; 1380 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>; 1381 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>; 1382 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>; 1383 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>; 1384 1385 // Extr patterns. 1386 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> : 1387 DSPPat<(i32 (OpNode GPR32:$rs, ACRegsDSP:$ac)), 1388 (Instr ACRegsDSP:$ac, GPR32:$rs)>; 1389 1390 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> : 1391 DSPPat<(i32 (OpNode immZExt5:$shift, ACRegsDSP:$ac)), 1392 (Instr ACRegsDSP:$ac, immZExt5:$shift)>; 1393 1394 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>; 1395 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>; 1396 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>; 1397 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>; 1398 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>; 1399 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>; 1400 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>; 1401 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>; 1402 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>; 1403 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>; 1404 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>; 1405 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>; 1406 1407 // mflo/hi patterns. 1408 let AddedComplexity = 20 in 1409 def : DSPPat<(i32 (ExtractLOHI ACRegsDSP:$ac, imm:$lohi_idx)), 1410 (EXTRACT_SUBREG ACRegsDSP:$ac, imm:$lohi_idx)>; 1411 1412 // Indexed load patterns. 1413 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> : 1414 DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))), 1415 (Instr i32:$base, i32:$index)>; 1416 1417 let AddedComplexity = 20 in { 1418 def : IndexedLoadPat<zextloadi8, LBUX>; 1419 def : IndexedLoadPat<sextloadi16, LHX>; 1420 def : IndexedLoadPat<load, LWX>; 1421 } 1422
