1 //===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the ARM register file 12 //===----------------------------------------------------------------------===// 13 14 // Registers are identified with 4-bit ID numbers. 15 class ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> { 16 let HWEncoding = Enc; 17 let Namespace = "ARM"; 18 let SubRegs = subregs; 19 // All bits of ARM registers with sub-registers are covered by sub-registers. 20 let CoveredBySubRegs = 1; 21 } 22 23 class ARMFReg<bits<16> Enc, string n> : Register<n> { 24 let HWEncoding = Enc; 25 let Namespace = "ARM"; 26 } 27 28 // Subregister indices. 29 let Namespace = "ARM" in { 30 def qqsub_0 : SubRegIndex<256>; 31 def qqsub_1 : SubRegIndex<256, 256>; 32 33 // Note: Code depends on these having consecutive numbers. 34 def qsub_0 : SubRegIndex<128>; 35 def qsub_1 : SubRegIndex<128, 128>; 36 def qsub_2 : ComposedSubRegIndex<qqsub_1, qsub_0>; 37 def qsub_3 : ComposedSubRegIndex<qqsub_1, qsub_1>; 38 39 def dsub_0 : SubRegIndex<64>; 40 def dsub_1 : SubRegIndex<64, 64>; 41 def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>; 42 def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>; 43 def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>; 44 def dsub_5 : ComposedSubRegIndex<qsub_2, dsub_1>; 45 def dsub_6 : ComposedSubRegIndex<qsub_3, dsub_0>; 46 def dsub_7 : ComposedSubRegIndex<qsub_3, dsub_1>; 47 48 def ssub_0 : SubRegIndex<32>; 49 def ssub_1 : SubRegIndex<32, 32>; 50 def ssub_2 : ComposedSubRegIndex<dsub_1, ssub_0>; 51 def ssub_3 : ComposedSubRegIndex<dsub_1, ssub_1>; 52 53 def gsub_0 : SubRegIndex<32>; 54 def gsub_1 : SubRegIndex<32, 32>; 55 // Let TableGen synthesize the remaining 12 ssub_* indices. 56 // We don't need to name them. 57 } 58 59 // Integer registers 60 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; 61 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; 62 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>; 63 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>; 64 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>; 65 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>; 66 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>; 67 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>; 68 // These require 32-bit instructions. 69 let CostPerUse = 1 in { 70 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>; 71 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>; 72 def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>; 73 def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>; 74 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>; 75 def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>; 76 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>; 77 def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>; 78 } 79 80 // Float registers 81 def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">; 82 def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">; 83 def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">; 84 def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">; 85 def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">; 86 def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">; 87 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">; 88 def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">; 89 def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">; 90 def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">; 91 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">; 92 def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">; 93 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">; 94 def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">; 95 def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; 96 def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">; 97 98 // Aliases of the F* registers used to hold 64-bit fp values (doubles) 99 let SubRegIndices = [ssub_0, ssub_1] in { 100 def D0 : ARMReg< 0, "d0", [S0, S1]>, DwarfRegNum<[256]>; 101 def D1 : ARMReg< 1, "d1", [S2, S3]>, DwarfRegNum<[257]>; 102 def D2 : ARMReg< 2, "d2", [S4, S5]>, DwarfRegNum<[258]>; 103 def D3 : ARMReg< 3, "d3", [S6, S7]>, DwarfRegNum<[259]>; 104 def D4 : ARMReg< 4, "d4", [S8, S9]>, DwarfRegNum<[260]>; 105 def D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>; 106 def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>; 107 def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>; 108 def D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>; 109 def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>; 110 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>; 111 def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>; 112 def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>; 113 def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>; 114 def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>; 115 def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>; 116 } 117 118 // VFP3 defines 16 additional double registers 119 def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>; 120 def D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>; 121 def D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>; 122 def D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>; 123 def D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>; 124 def D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>; 125 def D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>; 126 def D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>; 127 def D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>; 128 def D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>; 129 def D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>; 130 def D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>; 131 def D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>; 132 def D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>; 133 def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>; 134 def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>; 135 136 // Advanced SIMD (NEON) defines 16 quad-word aliases 137 let SubRegIndices = [dsub_0, dsub_1] in { 138 def Q0 : ARMReg< 0, "q0", [D0, D1]>; 139 def Q1 : ARMReg< 1, "q1", [D2, D3]>; 140 def Q2 : ARMReg< 2, "q2", [D4, D5]>; 141 def Q3 : ARMReg< 3, "q3", [D6, D7]>; 142 def Q4 : ARMReg< 4, "q4", [D8, D9]>; 143 def Q5 : ARMReg< 5, "q5", [D10, D11]>; 144 def Q6 : ARMReg< 6, "q6", [D12, D13]>; 145 def Q7 : ARMReg< 7, "q7", [D14, D15]>; 146 } 147 let SubRegIndices = [dsub_0, dsub_1] in { 148 def Q8 : ARMReg< 8, "q8", [D16, D17]>; 149 def Q9 : ARMReg< 9, "q9", [D18, D19]>; 150 def Q10 : ARMReg<10, "q10", [D20, D21]>; 151 def Q11 : ARMReg<11, "q11", [D22, D23]>; 152 def Q12 : ARMReg<12, "q12", [D24, D25]>; 153 def Q13 : ARMReg<13, "q13", [D26, D27]>; 154 def Q14 : ARMReg<14, "q14", [D28, D29]>; 155 def Q15 : ARMReg<15, "q15", [D30, D31]>; 156 } 157 158 // Current Program Status Register. 159 // We model fpscr with two registers: FPSCR models the control bits and will be 160 // reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV 161 // models the APSR when it's accessed by some special instructions. In such cases 162 // it has the same encoding as PC. 163 def CPSR : ARMReg<0, "cpsr">; 164 def APSR : ARMReg<1, "apsr">; 165 def APSR_NZCV : ARMReg<15, "apsr_nzcv">; 166 def SPSR : ARMReg<2, "spsr">; 167 def FPSCR : ARMReg<3, "fpscr">; 168 def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> { 169 let Aliases = [FPSCR]; 170 } 171 def ITSTATE : ARMReg<4, "itstate">; 172 173 // Special Registers - only available in privileged mode. 174 def FPSID : ARMReg<0, "fpsid">; 175 def MVFR1 : ARMReg<6, "mvfr1">; 176 def MVFR0 : ARMReg<7, "mvfr0">; 177 def FPEXC : ARMReg<8, "fpexc">; 178 def FPINST : ARMReg<9, "fpinst">; 179 def FPINST2 : ARMReg<10, "fpinst2">; 180 181 // Register classes. 182 // 183 // pc == Program Counter 184 // lr == Link Register 185 // sp == Stack Pointer 186 // r12 == ip (scratch) 187 // r7 == Frame Pointer (thumb-style backtraces) 188 // r9 == May be reserved as Thread Register 189 // r11 == Frame Pointer (arm-style backtraces) 190 // r10 == Stack Limit 191 // 192 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), 193 SP, LR, PC)> { 194 // Allocate LR as the first CSR since it is always saved anyway. 195 // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't 196 // know how to spill them. If we make our prologue/epilogue code smarter at 197 // some point, we can go back to using the above allocation orders for the 198 // Thumb1 instructions that know how to use hi regs. 199 let AltOrders = [(add LR, GPR), (trunc GPR, 8)]; 200 let AltOrderSelect = [{ 201 return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 202 }]; 203 } 204 205 // GPRs without the PC. Some ARM instructions do not allow the PC in 206 // certain operand slots, particularly as the destination. Primarily 207 // useful for disassembly. 208 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { 209 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 210 let AltOrderSelect = [{ 211 return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 212 }]; 213 } 214 215 // GPRs without the PC but with APSR. Some instructions allow accessing the 216 // APSR, while actually encoding PC in the register field. This is usefull 217 // for assembly and disassembly only. 218 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> { 219 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 220 let AltOrderSelect = [{ 221 return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 222 }]; 223 } 224 225 // GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the 226 // implied SP argument list. 227 // FIXME: It would be better to not use this at all and refactor the 228 // instructions to not have SP an an explicit argument. That makes 229 // frame index resolution a bit trickier, though. 230 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>; 231 232 // restricted GPR register class. Many Thumb2 instructions allow the full 233 // register range for operands, but have undefined behaviours when PC 234 // or SP (R13 or R15) are used. The ARM ISA refers to these operands 235 // via the BadReg() pseudo-code description. 236 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { 237 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)]; 238 let AltOrderSelect = [{ 239 return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 240 }]; 241 } 242 243 // Thumb registers are R0-R7 normally. Some instructions can still use 244 // the general GPR register class above (MOV, e.g.) 245 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>; 246 247 // The high registers in thumb mode, R8-R15. 248 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>; 249 250 // For tail calls, we can't use callee-saved registers, as they are restored 251 // to the saved value before the tail call, which would clobber a call address. 252 // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of 253 // this class and the preceding one(!) This is what we want. 254 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> { 255 let AltOrders = [(and tcGPR, tGPR)]; 256 let AltOrderSelect = [{ 257 return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 258 }]; 259 } 260 261 // Condition code registers. 262 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> { 263 let CopyCost = -1; // Don't allow copying of status registers. 264 let isAllocatable = 0; 265 } 266 267 // Scalar single precision floating point register class.. 268 // FIXME: Allocation order changed to s0, s2, s4, ... as a quick hack to 269 // avoid partial-write dependencies on D registers (S registers are 270 // renamed as portions of D registers). 271 def SPR : RegisterClass<"ARM", [f32], 32, (add (decimate 272 (sequence "S%u", 0, 31), 2), 273 (sequence "S%u", 0, 31))>; 274 275 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 276 // operations 277 def SPR_8 : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 15)>; 278 279 // Scalar double precision floating point / generic 64-bit vector register 280 // class. 281 // ARM requires only word alignment for double. It's more performant if it 282 // is double-word alignment though. 283 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, 284 (sequence "D%u", 0, 31)> { 285 // Allocate non-VFP2 registers D16-D31 first. 286 let AltOrders = [(rotl DPR, 16)]; 287 let AltOrderSelect = [{ return 1; }]; 288 } 289 290 // Subset of DPR that are accessible with VFP2 (and so that also have 291 // 32-bit SPR subregs). 292 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, 293 (trunc DPR, 16)>; 294 295 // Subset of DPR which can be used as a source of NEON scalars for 16-bit 296 // operations 297 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, 298 (trunc DPR, 8)>; 299 300 // Generic 128-bit vector register class. 301 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128, 302 (sequence "Q%u", 0, 15)> { 303 // Allocate non-VFP2 aliases Q8-Q15 first. 304 let AltOrders = [(rotl QPR, 8)]; 305 let AltOrderSelect = [{ return 1; }]; 306 } 307 308 // Subset of QPR that have 32-bit SPR subregs. 309 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 310 128, (trunc QPR, 8)>; 311 312 // Subset of QPR that have DPR_8 and SPR_8 subregs. 313 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 314 128, (trunc QPR, 4)>; 315 316 // Pseudo-registers representing odd-even pairs of D registers. The even-odd 317 // pairs are already represented by the Q registers. 318 // These are needed by NEON instructions requiring two consecutive D registers. 319 // There is no D31_D0 register as that is always an UNPREDICTABLE encoding. 320 def TuplesOE2D : RegisterTuples<[dsub_0, dsub_1], 321 [(decimate (shl DPR, 1), 2), 322 (decimate (shl DPR, 2), 2)]>; 323 324 // Register class representing a pair of consecutive D registers. 325 // Use the Q registers for the even-odd pairs. 326 def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 327 128, (interleave QPR, TuplesOE2D)> { 328 // Allocate starting at non-VFP2 registers D16-D31 first. 329 // Prefer even-odd pairs as they are easier to copy. 330 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))]; 331 let AltOrderSelect = [{ return 1; }]; 332 } 333 334 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP. 335 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs. 336 def Tuples2R : RegisterTuples<[gsub_0, gsub_1], 337 [(add R0, R2, R4, R6, R8, R10, R12), 338 (add R1, R3, R5, R7, R9, R11, SP)]>; 339 340 // Register class representing a pair of even-odd GPRs. 341 def GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2R)> { 342 let Size = 64; // 2 x 32 bits, we have no predefined type of that size. 343 } 344 345 // Pseudo-registers representing 3 consecutive D registers. 346 def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2], 347 [(shl DPR, 0), 348 (shl DPR, 1), 349 (shl DPR, 2)]>; 350 351 // 3 consecutive D registers. 352 def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> { 353 let Size = 192; // 3 x 64 bits, we have no predefined type of that size. 354 } 355 356 // Pseudo 256-bit registers to represent pairs of Q registers. These should 357 // never be present in the emitted code. 358 // These are used for NEON load / store instructions, e.g., vld4, vst3. 359 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>; 360 361 // Pseudo 256-bit vector register class to model pairs of Q registers 362 // (4 consecutive D registers). 363 def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> { 364 // Allocate non-VFP2 aliases first. 365 let AltOrders = [(rotl QQPR, 8)]; 366 let AltOrderSelect = [{ return 1; }]; 367 } 368 369 // Tuples of 4 D regs that isn't also a pair of Q regs. 370 def TuplesOE4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3], 371 [(decimate (shl DPR, 1), 2), 372 (decimate (shl DPR, 2), 2), 373 (decimate (shl DPR, 3), 2), 374 (decimate (shl DPR, 4), 2)]>; 375 376 // 4 consecutive D registers. 377 def DQuad : RegisterClass<"ARM", [v4i64], 256, 378 (interleave Tuples2Q, TuplesOE4D)>; 379 380 // Pseudo 512-bit registers to represent four consecutive Q registers. 381 def Tuples2QQ : RegisterTuples<[qqsub_0, qqsub_1], 382 [(shl QQPR, 0), (shl QQPR, 2)]>; 383 384 // Pseudo 512-bit vector register class to model 4 consecutive Q registers 385 // (8 consecutive D registers). 386 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> { 387 // Allocate non-VFP2 aliases first. 388 let AltOrders = [(rotl QQQQPR, 8)]; 389 let AltOrderSelect = [{ return 1; }]; 390 } 391 392 393 // Pseudo-registers representing 2-spaced consecutive D registers. 394 def Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2], 395 [(shl DPR, 0), 396 (shl DPR, 2)]>; 397 398 // Spaced pairs of D registers. 399 def DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>; 400 401 def Tuples3DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4], 402 [(shl DPR, 0), 403 (shl DPR, 2), 404 (shl DPR, 4)]>; 405 406 // Spaced triples of D registers. 407 def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> { 408 let Size = 192; // 3 x 64 bits, we have no predefined type of that size. 409 } 410 411 def Tuples4DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4, dsub_6], 412 [(shl DPR, 0), 413 (shl DPR, 2), 414 (shl DPR, 4), 415 (shl DPR, 6)]>; 416 417 // Spaced quads of D registers. 418 def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>; 419
