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      1 //===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the Hexagon specific subclass of TargetSubtarget.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "HexagonSubtarget.h"
     15 #include "Hexagon.h"
     16 #include "HexagonRegisterInfo.h"
     17 #include "llvm/Support/CommandLine.h"
     18 #include "llvm/Support/ErrorHandling.h"
     19 using namespace llvm;
     20 
     21 #define GET_SUBTARGETINFO_CTOR
     22 #define GET_SUBTARGETINFO_TARGET_DESC
     23 #include "HexagonGenSubtargetInfo.inc"
     24 
     25 static cl::opt<bool>
     26 EnableV3("enable-hexagon-v3", cl::Hidden,
     27          cl::desc("Enable Hexagon V3 instructions."));
     28 
     29 static cl::opt<bool>
     30 EnableMemOps(
     31     "enable-hexagon-memops",
     32     cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
     33     cl::desc(
     34       "Generate V4 MEMOP in code generation for Hexagon target"));
     35 
     36 static cl::opt<bool>
     37 DisableMemOps(
     38     "disable-hexagon-memops",
     39     cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
     40     cl::desc(
     41       "Do not generate V4 MEMOP in code generation for Hexagon target"));
     42 
     43 static cl::opt<bool>
     44 EnableIEEERndNear(
     45     "enable-hexagon-ieee-rnd-near",
     46     cl::Hidden, cl::ZeroOrMore, cl::init(false),
     47     cl::desc("Generate non-chopped conversion from fp to int."));
     48 
     49 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
     50   HexagonGenSubtargetInfo(TT, CPU, FS),
     51   CPUString(CPU.str()) {
     52 
     53   // If the programmer has not specified a Hexagon version, default to -mv4.
     54   if (CPUString.empty())
     55     CPUString = "hexagonv4";
     56 
     57   if (CPUString == "hexagonv2") {
     58     HexagonArchVersion = V2;
     59   } else if (CPUString == "hexagonv3") {
     60     EnableV3 = true;
     61     HexagonArchVersion = V3;
     62   } else if (CPUString == "hexagonv4") {
     63     HexagonArchVersion = V4;
     64   } else if (CPUString == "hexagonv5") {
     65     HexagonArchVersion = V5;
     66   } else {
     67     llvm_unreachable("Unrecognized Hexagon processor version");
     68   }
     69 
     70   ParseSubtargetFeatures(CPUString, FS);
     71 
     72   // Initialize scheduling itinerary for the specified CPU.
     73   InstrItins = getInstrItineraryForCPU(CPUString);
     74 
     75   // UseMemOps on by default unless disabled explicitly
     76   if (DisableMemOps)
     77     UseMemOps = false;
     78   else if (EnableMemOps)
     79     UseMemOps = true;
     80   else
     81     UseMemOps = false;
     82 
     83   if (EnableIEEERndNear)
     84     ModeIEEERndNear = true;
     85   else
     86     ModeIEEERndNear = false;
     87 }
     88 
     89