Home | History | Annotate | Download | only in Hexagon 
      1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // Implements the info about Hexagon target spec.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "HexagonTargetMachine.h"
     15 #include "Hexagon.h"
     16 #include "HexagonISelLowering.h"
     17 #include "HexagonMachineScheduler.h"
     18 #include "HexagonTargetObjectFile.h"
     19 #include "llvm/CodeGen/Passes.h"
     20 #include "llvm/IR/Module.h"
     21 #include "llvm/PassManager.h"
     22 #include "llvm/Support/CommandLine.h"
     23 #include "llvm/Support/TargetRegistry.h"
     24 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
     25 #include "llvm/Transforms/Scalar.h"
     26 
     27 using namespace llvm;
     28 
     29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
     30       cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
     31 
     32 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
     33       cl::Hidden, cl::ZeroOrMore, cl::init(false),
     34       cl::desc("Disable Hexagon MI Scheduling"));
     35 
     36 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
     37       cl::Hidden, cl::ZeroOrMore, cl::init(false),
     38       cl::desc("Disable Hexagon CFG Optimization"));
     39 
     40 
     41 /// HexagonTargetMachineModule - Note that this is used on hosts that
     42 /// cannot link in a library unless there are references into the
     43 /// library.  In particular, it seems that it is not possible to get
     44 /// things to work on Win32 without this.  Though it is unused, do not
     45 /// remove it.
     46 extern "C" int HexagonTargetMachineModule;
     47 int HexagonTargetMachineModule = 0;
     48 
     49 extern "C" void LLVMInitializeHexagonTarget() {
     50   // Register the target.
     51   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
     52 }
     53 
     54 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
     55   return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler());
     56 }
     57 
     58 static MachineSchedRegistry
     59 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
     60                     createVLIWMachineSched);
     61 
     62 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
     63 ///
     64 
     65 /// Hexagon_TODO: Do I need an aggregate alignment?
     66 ///
     67 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
     68                                            StringRef CPU, StringRef FS,
     69                                            const TargetOptions &Options,
     70                                            Reloc::Model RM,
     71                                            CodeModel::Model CM,
     72                                            CodeGenOpt::Level OL)
     73   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
     74     DL("e-p:32:32:32-"
     75                 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
     76                 "f64:64:64-f32:32:32-a0:0-n32") ,
     77     Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
     78     TSInfo(*this),
     79     FrameLowering(Subtarget),
     80     InstrItins(&Subtarget.getInstrItineraryData()) {
     81     setMCUseCFI(false);
     82     initAsmInfo();
     83 }
     84 
     85 // addPassesForOptimizations - Allow the backend (target) to add Target
     86 // Independent Optimization passes to the Pass Manager.
     87 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
     88   if (getOptLevel() != CodeGenOpt::None) {
     89     PM.add(createConstantPropagationPass());
     90     PM.add(createLoopSimplifyPass());
     91     PM.add(createDeadCodeEliminationPass());
     92     PM.add(createConstantPropagationPass());
     93     PM.add(createLoopUnrollPass());
     94     PM.add(createLoopStrengthReducePass());
     95   }
     96   return true;
     97 }
     98 
     99 namespace {
    100 /// Hexagon Code Generator Pass Configuration Options.
    101 class HexagonPassConfig : public TargetPassConfig {
    102 public:
    103   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
    104     : TargetPassConfig(TM, PM) {
    105     // Enable MI scheduler.
    106     if (!DisableHexagonMISched) {
    107       enablePass(&MachineSchedulerID);
    108       MachineSchedRegistry::setDefault(createVLIWMachineSched);
    109     }
    110   }
    111 
    112   HexagonTargetMachine &getHexagonTargetMachine() const {
    113     return getTM<HexagonTargetMachine>();
    114   }
    115 
    116   virtual bool addInstSelector();
    117   virtual bool addPreRegAlloc();
    118   virtual bool addPostRegAlloc();
    119   virtual bool addPreSched2();
    120   virtual bool addPreEmitPass();
    121 };
    122 } // namespace
    123 
    124 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
    125   return new HexagonPassConfig(this, PM);
    126 }
    127 
    128 bool HexagonPassConfig::addInstSelector() {
    129   HexagonTargetMachine &TM = getHexagonTargetMachine();
    130   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
    131 
    132   if (!NoOpt)
    133     addPass(createHexagonRemoveExtendArgs(TM));
    134 
    135   addPass(createHexagonISelDag(TM, getOptLevel()));
    136 
    137   if (!NoOpt) {
    138     addPass(createHexagonPeephole());
    139     printAndVerify("After hexagon peephole pass");
    140   }
    141 
    142   return false;
    143 }
    144 
    145 bool HexagonPassConfig::addPreRegAlloc() {
    146   if (getOptLevel() != CodeGenOpt::None)
    147     if (!DisableHardwareLoops)
    148       addPass(createHexagonHardwareLoops());
    149   return false;
    150 }
    151 
    152 bool HexagonPassConfig::addPostRegAlloc() {
    153   const HexagonTargetMachine &TM = getHexagonTargetMachine();
    154   if (getOptLevel() != CodeGenOpt::None)
    155     if (!DisableHexagonCFGOpt)
    156       addPass(createHexagonCFGOptimizer(TM));
    157   return false;
    158 }
    159 
    160 bool HexagonPassConfig::addPreSched2() {
    161   const HexagonTargetMachine &TM = getHexagonTargetMachine();
    162   const HexagonTargetObjectFile &TLOF =
    163     (const HexagonTargetObjectFile &)getTargetLowering()->getObjFileLowering();
    164 
    165   addPass(createHexagonCopyToCombine());
    166   if (getOptLevel() != CodeGenOpt::None)
    167     addPass(&IfConverterID);
    168   if (!TLOF.IsSmallDataEnabled()) {
    169     addPass(createHexagonSplitConst32AndConst64(TM));
    170     printAndVerify("After hexagon split const32/64 pass");
    171   }
    172   return true;
    173 }
    174 
    175 bool HexagonPassConfig::addPreEmitPass() {
    176   const HexagonTargetMachine &TM = getHexagonTargetMachine();
    177   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
    178 
    179   if (!NoOpt)
    180     addPass(createHexagonNewValueJump());
    181 
    182   // Expand Spill code for predicate registers.
    183   addPass(createHexagonExpandPredSpillCode(TM));
    184 
    185   // Split up TFRcondsets into conditional transfers.
    186   addPass(createHexagonSplitTFRCondSets(TM));
    187 
    188   // Create Packets.
    189   if (!NoOpt) {
    190     if (!DisableHardwareLoops)
    191       addPass(createHexagonFixupHwLoops());
    192     addPass(createHexagonPacketizer());
    193   }
    194 
    195   return false;
    196 }
    197