1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the MIPS register file 12 //===----------------------------------------------------------------------===// 13 let Namespace = "Mips" in { 14 def sub_fpeven : SubRegIndex<32>; 15 def sub_fpodd : SubRegIndex<32, 32>; 16 def sub_32 : SubRegIndex<32>; 17 def sub_lo : SubRegIndex<32>; 18 def sub_hi : SubRegIndex<32, 32>; 19 def sub_dsp16_19 : SubRegIndex<4, 16>; 20 def sub_dsp20 : SubRegIndex<1, 20>; 21 def sub_dsp21 : SubRegIndex<1, 21>; 22 def sub_dsp22 : SubRegIndex<1, 22>; 23 def sub_dsp23 : SubRegIndex<1, 23>; 24 } 25 26 class Unallocatable { 27 bit isAllocatable = 0; 28 } 29 30 // We have banks of 32 registers each. 31 class MipsReg<bits<16> Enc, string n> : Register<n> { 32 let HWEncoding = Enc; 33 let Namespace = "Mips"; 34 } 35 36 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 37 : RegisterWithSubRegs<n, subregs> { 38 let HWEncoding = Enc; 39 let Namespace = "Mips"; 40 } 41 42 // Mips CPU Registers 43 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 44 45 // Mips 64-bit CPU Registers 46 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 47 : MipsRegWithSubRegs<Enc, n, subregs> { 48 let SubRegIndices = [sub_32]; 49 } 50 51 // Mips 32-bit FPU Registers 52 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 53 54 // Mips 64-bit (aliased) FPU Registers 55 class AFPR<bits<16> Enc, string n, list<Register> subregs> 56 : MipsRegWithSubRegs<Enc, n, subregs> { 57 let SubRegIndices = [sub_fpeven, sub_fpodd]; 58 let CoveredBySubRegs = 1; 59 } 60 61 class AFPR64<bits<16> Enc, string n, list<Register> subregs> 62 : MipsRegWithSubRegs<Enc, n, subregs> { 63 let SubRegIndices = [sub_32]; 64 } 65 66 // Accumulator Registers 67 class ACC<bits<16> Enc, string n, list<Register> subregs> 68 : MipsRegWithSubRegs<Enc, n, subregs> { 69 let SubRegIndices = [sub_lo, sub_hi]; 70 let CoveredBySubRegs = 1; 71 } 72 73 // Mips Hardware Registers 74 class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 75 76 //===----------------------------------------------------------------------===// 77 // Registers 78 //===----------------------------------------------------------------------===// 79 80 let Namespace = "Mips" in { 81 // General Purpose Registers 82 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 83 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 84 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 85 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 86 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 87 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 88 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 89 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 90 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 91 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 92 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 93 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 94 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 95 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 96 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 97 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 98 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 99 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 100 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 101 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 102 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 103 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 104 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 105 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 106 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 107 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 108 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 109 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 110 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 111 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 112 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 113 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 114 115 // General Purpose 64-bit Registers 116 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 117 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 118 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 119 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 120 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 121 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 122 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 123 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 124 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 125 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 126 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 127 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 128 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 129 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 130 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 131 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 132 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 133 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 134 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 135 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 136 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 137 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 138 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 139 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 140 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 141 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 142 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 143 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 144 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 145 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 146 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 147 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 148 149 /// Mips Single point precision FPU Registers 150 foreach I = 0-31 in 151 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 152 153 /// Mips Double point precision FPU Registers (aliased 154 /// with the single precision to hold 64 bit values) 155 foreach I = 0-15 in 156 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1), 157 [!cast<FPR>("F"#!shl(I, 1)), 158 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 159 160 /// Mips Double point precision FPU Registers in MFP64 mode. 161 foreach I = 0-31 in 162 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I)]>, 163 DwarfRegNum<[!add(I, 32)]>; 164 165 // Hi/Lo registers 166 def HI : Register<"ac0">, DwarfRegNum<[64]>; 167 def HI1 : Register<"ac1">, DwarfRegNum<[176]>; 168 def HI2 : Register<"ac2">, DwarfRegNum<[178]>; 169 def HI3 : Register<"ac3">, DwarfRegNum<[180]>; 170 def LO : Register<"ac0">, DwarfRegNum<[65]>; 171 def LO1 : Register<"ac1">, DwarfRegNum<[177]>; 172 def LO2 : Register<"ac2">, DwarfRegNum<[179]>; 173 def LO3 : Register<"ac3">, DwarfRegNum<[181]>; 174 175 let SubRegIndices = [sub_32] in { 176 def HI64 : RegisterWithSubRegs<"hi", [HI]>; 177 def LO64 : RegisterWithSubRegs<"lo", [LO]>; 178 } 179 180 // FP control registers. 181 foreach I = 0-31 in 182 def FCR#I : MipsReg<#I, ""#I>; 183 184 // FP condition code registers. 185 foreach I = 0-7 in 186 def FCC#I : MipsReg<#I, "fcc"#I>; 187 188 // PC register 189 def PC : Register<"pc">; 190 191 // Hardware register $29 192 def HWR29 : MipsReg<29, "29">; 193 def HWR29_64 : MipsReg<29, "29">; 194 195 // Accum registers 196 def AC0 : ACC<0, "ac0", [LO, HI]>; 197 def AC1 : ACC<1, "ac1", [LO1, HI1]>; 198 def AC2 : ACC<2, "ac2", [LO2, HI2]>; 199 def AC3 : ACC<3, "ac3", [LO3, HI3]>; 200 201 def AC0_64 : ACC<0, "ac0", [LO64, HI64]>; 202 203 // DSP-ASE control register fields. 204 def DSPPos : Register<"">; 205 def DSPSCount : Register<"">; 206 def DSPCarry : Register<"">; 207 def DSPEFI : Register<"">; 208 def DSPOutFlag16_19 : Register<"">; 209 def DSPOutFlag20 : Register<"">; 210 def DSPOutFlag21 : Register<"">; 211 def DSPOutFlag22 : Register<"">; 212 def DSPOutFlag23 : Register<"">; 213 def DSPCCond : Register<"">; 214 215 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 216 sub_dsp23] in 217 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 218 DSPOutFlag21, DSPOutFlag22, 219 DSPOutFlag23]>; 220 } 221 222 //===----------------------------------------------------------------------===// 223 // Register Classes 224 //===----------------------------------------------------------------------===// 225 226 class GPR32Class<list<ValueType> regTypes> : 227 RegisterClass<"Mips", regTypes, 32, (add 228 // Reserved 229 ZERO, AT, 230 // Return Values and Arguments 231 V0, V1, A0, A1, A2, A3, 232 // Not preserved across procedure calls 233 T0, T1, T2, T3, T4, T5, T6, T7, 234 // Callee save 235 S0, S1, S2, S3, S4, S5, S6, S7, 236 // Not preserved across procedure calls 237 T8, T9, 238 // Reserved 239 K0, K1, GP, SP, FP, RA)>; 240 241 def GPR32 : GPR32Class<[i32]>; 242 def DSPRegs : GPR32Class<[v4i8, v2i16]>; 243 244 def GPR64 : RegisterClass<"Mips", [i64], 64, (add 245 // Reserved 246 ZERO_64, AT_64, 247 // Return Values and Arguments 248 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 249 // Not preserved across procedure calls 250 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 251 // Callee save 252 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 253 // Not preserved across procedure calls 254 T8_64, T9_64, 255 // Reserved 256 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 257 258 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 259 // Return Values and Arguments 260 V0, V1, A0, A1, A2, A3, 261 // Callee save 262 S0, S1)>; 263 264 def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add 265 // Return Values and Arguments 266 V0, V1, A0, A1, A2, A3, 267 // Callee save 268 S0, S1, 269 SP)>; 270 271 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 272 273 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 274 275 // 64bit fp: 276 // * FGR64 - 32 64-bit registers 277 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 278 // 279 // 32bit fp: 280 // * FGR32 - 16 32-bit even registers 281 // * FGR32 - 32 32-bit registers (single float only mode) 282 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 283 284 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 285 // Return Values and Arguments 286 D0, D1, 287 // Not preserved across procedure calls 288 D2, D3, D4, D5, 289 // Return Values and Arguments 290 D6, D7, 291 // Not preserved across procedure calls 292 D8, D9, 293 // Callee save 294 D10, D11, D12, D13, D14, D15)>; 295 296 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 297 298 // FP control registers. 299 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, 300 Unallocatable; 301 302 // FP condition code registers. 303 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, 304 Unallocatable; 305 306 // Hi/Lo Registers 307 def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>; 308 def HIRegs : RegisterClass<"Mips", [i32], 32, (add HI)>; 309 def LORegsDSP : RegisterClass<"Mips", [i32], 32, (add LO, LO1, LO2, LO3)>; 310 def HIRegsDSP : RegisterClass<"Mips", [i32], 32, (add HI, HI1, HI2, HI3)>; 311 def LORegs64 : RegisterClass<"Mips", [i64], 64, (add LO64)>; 312 def HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>; 313 314 // Hardware registers 315 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 316 def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable; 317 318 // Accumulator Registers 319 def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 320 let Size = 64; 321 } 322 323 def ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 324 let Size = 128; 325 } 326 327 def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 328 let Size = 64; 329 } 330 331 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 332 333 // Register Operands. 334 335 class MipsAsmRegOperand : AsmOperandClass { 336 let RenderMethod = "addRegAsmOperands"; 337 } 338 def GPR32AsmOperand : MipsAsmRegOperand { 339 let Name = "GPR32Asm"; 340 let ParserMethod = "parseGPR32"; 341 } 342 343 def GPR64AsmOperand : MipsAsmRegOperand { 344 let Name = "GPR64Asm"; 345 let ParserMethod = "parseGPR64"; 346 } 347 348 def ACRegsDSPAsmOperand : MipsAsmRegOperand { 349 let Name = "ACRegsDSPAsm"; 350 let ParserMethod = "parseACRegsDSP"; 351 } 352 353 def CCRAsmOperand : MipsAsmRegOperand { 354 let Name = "CCRAsm"; 355 let ParserMethod = "parseCCRRegs"; 356 } 357 358 def AFGR64AsmOperand : MipsAsmRegOperand { 359 let Name = "AFGR64Asm"; 360 let ParserMethod = "parseAFGR64Regs"; 361 } 362 363 def FGR64AsmOperand : MipsAsmRegOperand { 364 let Name = "FGR64Asm"; 365 let ParserMethod = "parseFGR64Regs"; 366 } 367 368 def FGR32AsmOperand : MipsAsmRegOperand { 369 let Name = "FGR32Asm"; 370 let ParserMethod = "parseFGR32Regs"; 371 } 372 373 def FCCRegsAsmOperand : MipsAsmRegOperand { 374 let Name = "FCCRegsAsm"; 375 let ParserMethod = "parseFCCRegs"; 376 } 377 378 def GPR32Opnd : RegisterOperand<GPR32> { 379 let ParserMatchClass = GPR32AsmOperand; 380 } 381 382 def GPR64Opnd : RegisterOperand<GPR64> { 383 let ParserMatchClass = GPR64AsmOperand; 384 } 385 386 def CCROpnd : RegisterOperand<CCR> { 387 let ParserMatchClass = CCRAsmOperand; 388 } 389 390 def HWRegsAsmOperand : MipsAsmRegOperand { 391 let Name = "HWRegsAsm"; 392 let ParserMethod = "parseHWRegs"; 393 } 394 395 def HW64RegsAsmOperand : MipsAsmRegOperand { 396 let Name = "HW64RegsAsm"; 397 let ParserMethod = "parseHW64Regs"; 398 } 399 400 def HWRegsOpnd : RegisterOperand<HWRegs> { 401 let ParserMatchClass = HWRegsAsmOperand; 402 } 403 404 def HW64RegsOpnd : RegisterOperand<HWRegs64> { 405 let ParserMatchClass = HW64RegsAsmOperand; 406 } 407 408 def AFGR64RegsOpnd : RegisterOperand<AFGR64> { 409 let ParserMatchClass = AFGR64AsmOperand; 410 } 411 412 def FGR64RegsOpnd : RegisterOperand<FGR64> { 413 let ParserMatchClass = FGR64AsmOperand; 414 } 415 416 def FGR32RegsOpnd : RegisterOperand<FGR32> { 417 let ParserMatchClass = FGR32AsmOperand; 418 } 419 420 def FCCRegsOpnd : RegisterOperand<FCC> { 421 let ParserMatchClass = FCCRegsAsmOperand; 422 } 423 424 def ACRegsDSPOpnd : RegisterOperand<ACRegsDSP> { 425 let ParserMatchClass = ACRegsDSPAsmOperand; 426 } 427
