1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains DAG node defintions for the AMDGPU target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // AMDGPU DAG Profiles 16 //===----------------------------------------------------------------------===// 17 18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [ 19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 20 ]>; 21 22 //===----------------------------------------------------------------------===// 23 // AMDGPU DAG Nodes 24 // 25 26 // This argument to this node is a dword address. 27 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>; 28 29 // out = a - floor(a) 30 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>; 31 32 // out = max(a, b) a and b are floats 33 def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp, 34 [SDNPCommutative, SDNPAssociative] 35 >; 36 37 // out = max(a, b) a and b are signed ints 38 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp, 39 [SDNPCommutative, SDNPAssociative] 40 >; 41 42 // out = max(a, b) a and b are unsigned ints 43 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp, 44 [SDNPCommutative, SDNPAssociative] 45 >; 46 47 // out = min(a, b) a and b are floats 48 def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp, 49 [SDNPCommutative, SDNPAssociative] 50 >; 51 52 // out = min(a, b) a snd b are signed ints 53 def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp, 54 [SDNPCommutative, SDNPAssociative] 55 >; 56 57 // out = min(a, b) a and b are unsigned ints 58 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp, 59 [SDNPCommutative, SDNPAssociative] 60 >; 61 62 // urecip - This operation is a helper for integer division, it returns the 63 // result of 1 / a as a fractional unsigned integer. 64 // out = (2^32 / a) + e 65 // e is rounding error 66 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>; 67 68 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD", 69 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>, 70 [SDNPHasChain, SDNPMayLoad]>; 71 72 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE", 73 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>, 74 [SDNPHasChain, SDNPMayStore]>; 75
