1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // SI Instruction format definitions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : 15 AMDGPUInst<outs, ins, asm, pattern> { 16 17 field bits<1> VM_CNT = 0; 18 field bits<1> EXP_CNT = 0; 19 field bits<1> LGKM_CNT = 0; 20 21 let TSFlags{0} = VM_CNT; 22 let TSFlags{1} = EXP_CNT; 23 let TSFlags{2} = LGKM_CNT; 24 } 25 26 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> : 27 InstSI <outs, ins, asm, pattern> { 28 29 field bits<32> Inst; 30 let Size = 4; 31 } 32 33 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> : 34 InstSI <outs, ins, asm, pattern> { 35 36 field bits<64> Inst; 37 let Size = 8; 38 } 39 40 //===----------------------------------------------------------------------===// 41 // Scalar operations 42 //===----------------------------------------------------------------------===// 43 44 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 45 Enc32<outs, ins, asm, pattern> { 46 47 bits<7> SDST; 48 bits<8> SSRC0; 49 50 let Inst{7-0} = SSRC0; 51 let Inst{15-8} = op; 52 let Inst{22-16} = SDST; 53 let Inst{31-23} = 0x17d; //encoding; 54 55 let mayLoad = 0; 56 let mayStore = 0; 57 let hasSideEffects = 0; 58 } 59 60 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 61 Enc32 <outs, ins, asm, pattern> { 62 63 bits<7> SDST; 64 bits<8> SSRC0; 65 bits<8> SSRC1; 66 67 let Inst{7-0} = SSRC0; 68 let Inst{15-8} = SSRC1; 69 let Inst{22-16} = SDST; 70 let Inst{29-23} = op; 71 let Inst{31-30} = 0x2; // encoding 72 73 let mayLoad = 0; 74 let mayStore = 0; 75 let hasSideEffects = 0; 76 } 77 78 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 79 Enc32<outs, ins, asm, pattern> { 80 81 bits<8> SSRC0; 82 bits<8> SSRC1; 83 84 let Inst{7-0} = SSRC0; 85 let Inst{15-8} = SSRC1; 86 let Inst{22-16} = op; 87 let Inst{31-23} = 0x17e; 88 89 let DisableEncoding = "$dst"; 90 let mayLoad = 0; 91 let mayStore = 0; 92 let hasSideEffects = 0; 93 } 94 95 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> : 96 Enc32 <outs, ins , asm, pattern> { 97 98 bits <7> SDST; 99 bits <16> SIMM16; 100 101 let Inst{15-0} = SIMM16; 102 let Inst{22-16} = SDST; 103 let Inst{27-23} = op; 104 let Inst{31-28} = 0xb; //encoding 105 106 let mayLoad = 0; 107 let mayStore = 0; 108 let hasSideEffects = 0; 109 } 110 111 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 < 112 (outs), 113 ins, 114 asm, 115 pattern > { 116 117 bits <16> SIMM16; 118 119 let Inst{15-0} = SIMM16; 120 let Inst{22-16} = op; 121 let Inst{31-23} = 0x17f; // encoding 122 123 let mayLoad = 0; 124 let mayStore = 0; 125 let hasSideEffects = 0; 126 } 127 128 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm, 129 list<dag> pattern> : Enc32<outs, ins, asm, pattern> { 130 131 bits<7> SDST; 132 bits<7> SBASE; 133 bits<8> OFFSET; 134 135 let Inst{7-0} = OFFSET; 136 let Inst{8} = imm; 137 let Inst{14-9} = SBASE{6-1}; 138 let Inst{21-15} = SDST; 139 let Inst{26-22} = op; 140 let Inst{31-27} = 0x18; //encoding 141 142 let LGKM_CNT = 1; 143 } 144 145 //===----------------------------------------------------------------------===// 146 // Vector ALU operations 147 //===----------------------------------------------------------------------===// 148 149 let Uses = [EXEC] in { 150 151 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 152 Enc32 <outs, ins, asm, pattern> { 153 154 bits<8> VDST; 155 bits<9> SRC0; 156 157 let Inst{8-0} = SRC0; 158 let Inst{16-9} = op; 159 let Inst{24-17} = VDST; 160 let Inst{31-25} = 0x3f; //encoding 161 162 let mayLoad = 0; 163 let mayStore = 0; 164 let hasSideEffects = 0; 165 } 166 167 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : 168 Enc32 <outs, ins, asm, pattern> { 169 170 bits<8> VDST; 171 bits<9> SRC0; 172 bits<8> VSRC1; 173 174 let Inst{8-0} = SRC0; 175 let Inst{16-9} = VSRC1; 176 let Inst{24-17} = VDST; 177 let Inst{30-25} = op; 178 let Inst{31} = 0x0; //encoding 179 180 let mayLoad = 0; 181 let mayStore = 0; 182 let hasSideEffects = 0; 183 } 184 185 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : 186 Enc64 <outs, ins, asm, pattern> { 187 188 bits<8> dst; 189 bits<9> src0; 190 bits<9> src1; 191 bits<9> src2; 192 bits<3> abs; 193 bits<1> clamp; 194 bits<2> omod; 195 bits<3> neg; 196 197 let Inst{7-0} = dst; 198 let Inst{10-8} = abs; 199 let Inst{11} = clamp; 200 let Inst{25-17} = op; 201 let Inst{31-26} = 0x34; //encoding 202 let Inst{40-32} = src0; 203 let Inst{49-41} = src1; 204 let Inst{58-50} = src2; 205 let Inst{60-59} = omod; 206 let Inst{63-61} = neg; 207 208 let mayLoad = 0; 209 let mayStore = 0; 210 let hasSideEffects = 0; 211 } 212 213 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : 214 Enc64 <outs, ins, asm, pattern> { 215 216 bits<8> dst; 217 bits<9> src0; 218 bits<9> src1; 219 bits<9> src2; 220 bits<7> sdst; 221 bits<2> omod; 222 bits<3> neg; 223 224 let Inst{7-0} = dst; 225 let Inst{14-8} = sdst; 226 let Inst{25-17} = op; 227 let Inst{31-26} = 0x34; //encoding 228 let Inst{40-32} = src0; 229 let Inst{49-41} = src1; 230 let Inst{58-50} = src2; 231 let Inst{60-59} = omod; 232 let Inst{63-61} = neg; 233 234 let mayLoad = 0; 235 let mayStore = 0; 236 let hasSideEffects = 0; 237 } 238 239 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : 240 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> { 241 242 bits<9> SRC0; 243 bits<8> VSRC1; 244 245 let Inst{8-0} = SRC0; 246 let Inst{16-9} = VSRC1; 247 let Inst{24-17} = op; 248 let Inst{31-25} = 0x3e; 249 250 let DisableEncoding = "$dst"; 251 let mayLoad = 0; 252 let mayStore = 0; 253 let hasSideEffects = 0; 254 } 255 256 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> : 257 Enc32 <outs, ins, asm, pattern> { 258 259 bits<8> VDST; 260 bits<8> VSRC; 261 bits<2> ATTRCHAN; 262 bits<6> ATTR; 263 264 let Inst{7-0} = VSRC; 265 let Inst{9-8} = ATTRCHAN; 266 let Inst{15-10} = ATTR; 267 let Inst{17-16} = op; 268 let Inst{25-18} = VDST; 269 let Inst{31-26} = 0x32; // encoding 270 271 let neverHasSideEffects = 1; 272 let mayLoad = 1; 273 let mayStore = 0; 274 } 275 276 } // End Uses = [EXEC] 277 278 //===----------------------------------------------------------------------===// 279 // Vector I/O operations 280 //===----------------------------------------------------------------------===// 281 282 let Uses = [EXEC] in { 283 284 class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 285 Enc64 <outs, ins, asm, pattern> { 286 287 bits<8> vdst; 288 bits<1> gds; 289 bits<8> addr; 290 bits<8> data0; 291 bits<8> data1; 292 bits<8> offset0; 293 bits<8> offset1; 294 295 let Inst{7-0} = offset0; 296 let Inst{15-8} = offset1; 297 let Inst{17} = gds; 298 let Inst{25-18} = op; 299 let Inst{31-26} = 0x36; //encoding 300 let Inst{39-32} = addr; 301 let Inst{47-40} = data0; 302 let Inst{55-48} = data1; 303 let Inst{63-56} = vdst; 304 305 let LGKM_CNT = 1; 306 } 307 308 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 309 Enc64<outs, ins, asm, pattern> { 310 311 bits<12> offset; 312 bits<1> offen; 313 bits<1> idxen; 314 bits<1> glc; 315 bits<1> addr64; 316 bits<1> lds; 317 bits<8> vaddr; 318 bits<8> vdata; 319 bits<7> srsrc; 320 bits<1> slc; 321 bits<1> tfe; 322 bits<8> soffset; 323 324 let Inst{11-0} = offset; 325 let Inst{12} = offen; 326 let Inst{13} = idxen; 327 let Inst{14} = glc; 328 let Inst{15} = addr64; 329 let Inst{16} = lds; 330 let Inst{24-18} = op; 331 let Inst{31-26} = 0x38; //encoding 332 let Inst{39-32} = vaddr; 333 let Inst{47-40} = vdata; 334 let Inst{52-48} = srsrc{6-2}; 335 let Inst{54} = slc; 336 let Inst{55} = tfe; 337 let Inst{63-56} = soffset; 338 339 let VM_CNT = 1; 340 let EXP_CNT = 1; 341 342 let neverHasSideEffects = 1; 343 } 344 345 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> : 346 Enc64<outs, ins, asm, pattern> { 347 348 bits<8> VDATA; 349 bits<12> OFFSET; 350 bits<1> OFFEN; 351 bits<1> IDXEN; 352 bits<1> GLC; 353 bits<1> ADDR64; 354 bits<4> DFMT; 355 bits<3> NFMT; 356 bits<8> VADDR; 357 bits<7> SRSRC; 358 bits<1> SLC; 359 bits<1> TFE; 360 bits<8> SOFFSET; 361 362 let Inst{11-0} = OFFSET; 363 let Inst{12} = OFFEN; 364 let Inst{13} = IDXEN; 365 let Inst{14} = GLC; 366 let Inst{15} = ADDR64; 367 let Inst{18-16} = op; 368 let Inst{22-19} = DFMT; 369 let Inst{25-23} = NFMT; 370 let Inst{31-26} = 0x3a; //encoding 371 let Inst{39-32} = VADDR; 372 let Inst{47-40} = VDATA; 373 let Inst{52-48} = SRSRC{6-2}; 374 let Inst{54} = SLC; 375 let Inst{55} = TFE; 376 let Inst{63-56} = SOFFSET; 377 378 let VM_CNT = 1; 379 let EXP_CNT = 1; 380 381 let neverHasSideEffects = 1; 382 } 383 384 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 385 Enc64 <outs, ins, asm, pattern> { 386 387 bits<8> VDATA; 388 bits<4> DMASK; 389 bits<1> UNORM; 390 bits<1> GLC; 391 bits<1> DA; 392 bits<1> R128; 393 bits<1> TFE; 394 bits<1> LWE; 395 bits<1> SLC; 396 bits<8> VADDR; 397 bits<7> SRSRC; 398 bits<7> SSAMP; 399 400 let Inst{11-8} = DMASK; 401 let Inst{12} = UNORM; 402 let Inst{13} = GLC; 403 let Inst{14} = DA; 404 let Inst{15} = R128; 405 let Inst{16} = TFE; 406 let Inst{17} = LWE; 407 let Inst{24-18} = op; 408 let Inst{25} = SLC; 409 let Inst{31-26} = 0x3c; 410 let Inst{39-32} = VADDR; 411 let Inst{47-40} = VDATA; 412 let Inst{52-48} = SRSRC{6-2}; 413 let Inst{57-53} = SSAMP{6-2}; 414 415 let VM_CNT = 1; 416 let EXP_CNT = 1; 417 } 418 419 def EXP : Enc64< 420 (outs), 421 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm, 422 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), 423 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3", 424 [] > { 425 426 bits<4> EN; 427 bits<6> TGT; 428 bits<1> COMPR; 429 bits<1> DONE; 430 bits<1> VM; 431 bits<8> VSRC0; 432 bits<8> VSRC1; 433 bits<8> VSRC2; 434 bits<8> VSRC3; 435 436 let Inst{3-0} = EN; 437 let Inst{9-4} = TGT; 438 let Inst{10} = COMPR; 439 let Inst{11} = DONE; 440 let Inst{12} = VM; 441 let Inst{31-26} = 0x3e; 442 let Inst{39-32} = VSRC0; 443 let Inst{47-40} = VSRC1; 444 let Inst{55-48} = VSRC2; 445 let Inst{63-56} = VSRC3; 446 447 let EXP_CNT = 1; 448 } 449 450 } // End Uses = [EXEC] 451
