1 //===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains instruction definitions and patterns needed for 64-bit 11 // code generation on SPARC v9. 12 // 13 // Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can 14 // also be used in 32-bit code running on a SPARC v9 CPU. 15 // 16 //===----------------------------------------------------------------------===// 17 18 let Predicates = [Is64Bit] in { 19 // The same integer registers are used for i32 and i64 values. 20 // When registers hold i32 values, the high bits are don't care. 21 // This give us free trunc and anyext. 22 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>; 23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>; 24 25 } // Predicates = [Is64Bit] 26 27 28 //===----------------------------------------------------------------------===// 29 // 64-bit Shift Instructions. 30 //===----------------------------------------------------------------------===// 31 // 32 // The 32-bit shift instructions are still available. The left shift srl 33 // instructions shift all 64 bits, but it only accepts a 5-bit shift amount. 34 // 35 // The srl instructions only shift the low 32 bits and clear the high 32 bits. 36 // Finally, sra shifts the low 32 bits and sign-extends to 64 bits. 37 38 let Predicates = [Is64Bit] in { 39 40 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>; 41 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>; 42 43 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>; 44 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>; 45 46 defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>; 47 defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>; 48 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>; 49 50 } // Predicates = [Is64Bit] 51 52 53 //===----------------------------------------------------------------------===// 54 // 64-bit Immediates. 55 //===----------------------------------------------------------------------===// 56 // 57 // All 32-bit immediates can be materialized with sethi+or, but 64-bit 58 // immediates may require more code. There may be a point where it is 59 // preferable to use a constant pool load instead, depending on the 60 // microarchitecture. 61 62 // Single-instruction patterns. 63 64 // The ALU instructions want their simm13 operands as i32 immediates. 65 def as_i32imm : SDNodeXForm<imm, [{ 66 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32); 67 }]>; 68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>; 69 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>; 70 71 // Double-instruction patterns. 72 73 // All unsigned i32 immediates can be handled by sethi+or. 74 def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; 75 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>, 76 Requires<[Is64Bit]>; 77 78 // All negative i33 immediates can be handled by sethi+xor. 79 def nimm33 : PatLeaf<(imm), [{ 80 int64_t Imm = N->getSExtValue(); 81 return Imm < 0 && isInt<33>(Imm); 82 }]>; 83 // Bits 10-31 inverted. Same as assembler's %hix. 84 def HIX22 : SDNodeXForm<imm, [{ 85 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1); 86 return CurDAG->getTargetConstant(Val, MVT::i32); 87 }]>; 88 // Bits 0-9 with ones in bits 10-31. Same as assembler's %lox. 89 def LOX10 : SDNodeXForm<imm, [{ 90 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32); 91 }]>; 92 def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>, 93 Requires<[Is64Bit]>; 94 95 // More possible patterns: 96 // 97 // (sllx sethi, n) 98 // (sllx simm13, n) 99 // 100 // 3 instrs: 101 // 102 // (xor (sllx sethi), simm13) 103 // (sllx (xor sethi, simm13)) 104 // 105 // 4 instrs: 106 // 107 // (or sethi, (sllx sethi)) 108 // (xnor sethi, (sllx sethi)) 109 // 110 // 5 instrs: 111 // 112 // (or (sllx sethi), (or sethi, simm13)) 113 // (xnor (sllx sethi), (or sethi, simm13)) 114 // (or (sllx sethi), (sllx sethi)) 115 // (xnor (sllx sethi), (sllx sethi)) 116 // 117 // Worst case is 6 instrs: 118 // 119 // (or (sllx (or sethi, simmm13)), (or sethi, simm13)) 120 121 // Bits 42-63, same as assembler's %hh. 122 def HH22 : SDNodeXForm<imm, [{ 123 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1); 124 return CurDAG->getTargetConstant(Val, MVT::i32); 125 }]>; 126 // Bits 32-41, same as assembler's %hm. 127 def HM10 : SDNodeXForm<imm, [{ 128 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1); 129 return CurDAG->getTargetConstant(Val, MVT::i32); 130 }]>; 131 def : Pat<(i64 imm:$val), 132 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)), 133 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>, 134 Requires<[Is64Bit]>; 135 136 137 //===----------------------------------------------------------------------===// 138 // 64-bit Integer Arithmetic and Logic. 139 //===----------------------------------------------------------------------===// 140 141 let Predicates = [Is64Bit] in { 142 143 // Register-register instructions. 144 145 def : Pat<(and i64:$a, i64:$b), (ANDrr $a, $b)>; 146 def : Pat<(or i64:$a, i64:$b), (ORrr $a, $b)>; 147 def : Pat<(xor i64:$a, i64:$b), (XORrr $a, $b)>; 148 149 def : Pat<(and i64:$a, (not i64:$b)), (ANDNrr $a, $b)>; 150 def : Pat<(or i64:$a, (not i64:$b)), (ORNrr $a, $b)>; 151 def : Pat<(xor i64:$a, (not i64:$b)), (XNORrr $a, $b)>; 152 153 def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; 154 def : Pat<(sub i64:$a, i64:$b), (SUBrr $a, $b)>; 155 156 // Add/sub with carry were renamed to addc/subc in SPARC v9. 157 def : Pat<(adde i64:$a, i64:$b), (ADDXrr $a, $b)>; 158 def : Pat<(sube i64:$a, i64:$b), (SUBXrr $a, $b)>; 159 160 def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>; 161 def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>; 162 163 def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>; 164 165 // Register-immediate instructions. 166 167 def : Pat<(and i64:$a, (i64 simm13:$b)), (ANDri $a, (as_i32imm $b))>; 168 def : Pat<(or i64:$a, (i64 simm13:$b)), (ORri $a, (as_i32imm $b))>; 169 def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>; 170 171 def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>; 172 def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>; 173 174 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>; 175 176 } // Predicates = [Is64Bit] 177 178 179 //===----------------------------------------------------------------------===// 180 // 64-bit Integer Multiply and Divide. 181 //===----------------------------------------------------------------------===// 182 183 let Predicates = [Is64Bit] in { 184 185 def MULXrr : F3_1<2, 0b001001, 186 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 187 "mulx $rs1, $rs2, $rd", 188 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; 189 def MULXri : F3_2<2, 0b001001, 190 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i), 191 "mulx $rs1, $i, $rd", 192 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>; 193 194 // Division can trap. 195 let hasSideEffects = 1 in { 196 def SDIVXrr : F3_1<2, 0b101101, 197 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 198 "sdivx $rs1, $rs2, $rd", 199 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; 200 def SDIVXri : F3_2<2, 0b101101, 201 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i), 202 "sdivx $rs1, $i, $rd", 203 [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$i)))]>; 204 205 def UDIVXrr : F3_1<2, 0b001101, 206 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 207 "udivx $rs1, $rs2, $rd", 208 [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; 209 def UDIVXri : F3_2<2, 0b001101, 210 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i), 211 "udivx $rs1, $i, $rd", 212 [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$i)))]>; 213 } // hasSideEffects = 1 214 215 } // Predicates = [Is64Bit] 216 217 218 //===----------------------------------------------------------------------===// 219 // 64-bit Loads and Stores. 220 //===----------------------------------------------------------------------===// 221 // 222 // All the 32-bit loads and stores are available. The extending loads are sign 223 // or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits 224 // zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned 225 // Word). 226 // 227 // SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads. 228 229 let Predicates = [Is64Bit] in { 230 231 // 64-bit loads. 232 def LDXrr : F3_1<3, 0b001011, 233 (outs I64Regs:$dst), (ins MEMrr:$addr), 234 "ldx [$addr], $dst", 235 [(set i64:$dst, (load ADDRrr:$addr))]>; 236 def LDXri : F3_2<3, 0b001011, 237 (outs I64Regs:$dst), (ins MEMri:$addr), 238 "ldx [$addr], $dst", 239 [(set i64:$dst, (load ADDRri:$addr))]>; 240 241 // Extending loads to i64. 242 def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 243 def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 244 def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 245 def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 246 247 def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 248 def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 249 def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 250 def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 251 def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>; 252 def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>; 253 254 def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 255 def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 256 def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 257 def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 258 def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>; 259 def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>; 260 261 def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 262 def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 263 def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 264 def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 265 266 // Sign-extending load of i32 into i64 is a new SPARC v9 instruction. 267 def LDSWrr : F3_1<3, 0b001011, 268 (outs I64Regs:$dst), (ins MEMrr:$addr), 269 "ldsw [$addr], $dst", 270 [(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>; 271 def LDSWri : F3_2<3, 0b001011, 272 (outs I64Regs:$dst), (ins MEMri:$addr), 273 "ldsw [$addr], $dst", 274 [(set i64:$dst, (sextloadi32 ADDRri:$addr))]>; 275 276 // 64-bit stores. 277 def STXrr : F3_1<3, 0b001110, 278 (outs), (ins MEMrr:$addr, I64Regs:$src), 279 "stx $src, [$addr]", 280 [(store i64:$src, ADDRrr:$addr)]>; 281 def STXri : F3_2<3, 0b001110, 282 (outs), (ins MEMri:$addr, I64Regs:$src), 283 "stx $src, [$addr]", 284 [(store i64:$src, ADDRri:$addr)]>; 285 286 // Truncating stores from i64 are identical to the i32 stores. 287 def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>; 288 def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>; 289 def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>; 290 def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>; 291 def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>; 292 def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>; 293 294 // store 0, addr -> store %g0, addr 295 def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>; 296 def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>; 297 298 } // Predicates = [Is64Bit] 299 300 301 //===----------------------------------------------------------------------===// 302 // 64-bit Conditionals. 303 //===----------------------------------------------------------------------===// 304 // 305 // Flag-setting instructions like subcc and addcc set both icc and xcc flags. 306 // The icc flags correspond to the 32-bit result, and the xcc are for the 307 // full 64-bit result. 308 // 309 // We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for 310 // 64-bit compares. See LowerBR_CC. 311 312 let Predicates = [Is64Bit] in { 313 314 let Uses = [ICC] in 315 def BPXCC : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 316 "b$cc %xcc, $dst", 317 [(SPbrxcc bb:$dst, imm:$cc)]>; 318 319 // Conditional moves on %xcc. 320 let Uses = [ICC], Constraints = "$f = $rd" in { 321 def MOVXCCrr : Pseudo<(outs IntRegs:$rd), 322 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 323 "mov$cond %xcc, $rs2, $rd", 324 [(set i32:$rd, 325 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>; 326 def MOVXCCri : Pseudo<(outs IntRegs:$rd), 327 (ins i32imm:$i, IntRegs:$f, CCOp:$cond), 328 "mov$cond %xcc, $i, $rd", 329 [(set i32:$rd, 330 (SPselectxcc simm11:$i, i32:$f, imm:$cond))]>; 331 def FMOVS_XCC : Pseudo<(outs FPRegs:$rd), 332 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 333 "fmovs$cond %xcc, $rs2, $rd", 334 [(set f32:$rd, 335 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>; 336 def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd), 337 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 338 "fmovd$cond %xcc, $rs2, $rd", 339 [(set f64:$rd, 340 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; 341 } // Uses, Constraints 342 343 def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond), 344 (MOVXCCrr $t, $f, imm:$cond)>; 345 def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond), 346 (MOVXCCri (as_i32imm $t), $f, imm:$cond)>; 347 348 def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond), 349 (MOVICCrr $t, $f, imm:$cond)>; 350 def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond), 351 (MOVICCri (as_i32imm $t), $f, imm:$cond)>; 352 353 def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond), 354 (MOVFCCrr $t, $f, imm:$cond)>; 355 def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond), 356 (MOVFCCri (as_i32imm $t), $f, imm:$cond)>; 357 358 } // Predicates = [Is64Bit] 359
