1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Sparc instructions in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Instruction format superclass 16 //===----------------------------------------------------------------------===// 17 18 include "SparcInstrFormats.td" 19 20 //===----------------------------------------------------------------------===// 21 // Feature predicates. 22 //===----------------------------------------------------------------------===// 23 24 // True when generating 32-bit code. 25 def Is32Bit : Predicate<"!Subtarget.is64Bit()">; 26 27 // True when generating 64-bit code. This also implies HasV9. 28 def Is64Bit : Predicate<"Subtarget.is64Bit()">; 29 30 // HasV9 - This predicate is true when the target processor supports V9 31 // instructions. Note that the machine may be running in 32-bit mode. 32 def HasV9 : Predicate<"Subtarget.isV9()">; 33 34 // HasNoV9 - This predicate is true when the target doesn't have V9 35 // instructions. Use of this is just a hack for the isel not having proper 36 // costs for V8 instructions that are more expensive than their V9 ones. 37 def HasNoV9 : Predicate<"!Subtarget.isV9()">; 38 39 // HasVIS - This is true when the target processor has VIS extensions. 40 def HasVIS : Predicate<"Subtarget.isVIS()">; 41 42 // UseDeprecatedInsts - This predicate is true when the target processor is a 43 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough 44 // to use when appropriate. In either of these cases, the instruction selector 45 // will pick deprecated instructions. 46 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 47 48 //===----------------------------------------------------------------------===// 49 // Instruction Pattern Stuff 50 //===----------------------------------------------------------------------===// 51 52 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 53 54 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 55 56 def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 58 MVT::i32); 59 }]>; 60 61 def HI22 : SDNodeXForm<imm, [{ 62 // Transformation function: shift the immediate value down into the low bits. 63 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 64 }]>; 65 66 def SETHIimm : PatLeaf<(imm), [{ 67 return isShiftedUInt<22, 10>(N->getZExtValue()); 68 }], HI22>; 69 70 // Addressing modes. 71 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 72 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 73 74 // Address operands 75 def MEMrr : Operand<iPTR> { 76 let PrintMethod = "printMemOperand"; 77 let MIOperandInfo = (ops ptr_rc, ptr_rc); 78 } 79 def MEMri : Operand<iPTR> { 80 let PrintMethod = "printMemOperand"; 81 let MIOperandInfo = (ops ptr_rc, i32imm); 82 } 83 84 // Branch targets have OtherVT type. 85 def brtarget : Operand<OtherVT>; 86 def calltarget : Operand<i32>; 87 88 // Operand for printing out a condition code. 89 let PrintMethod = "printCCOperand" in 90 def CCOp : Operand<i32>; 91 92 def SDTSPcmpicc : 93 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 94 def SDTSPcmpfcc : 95 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 96 def SDTSPbrcc : 97 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 98 def SDTSPselectcc : 99 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 100 def SDTSPFTOI : 101 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 102 def SDTSPITOF : 103 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 104 105 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 106 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 107 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 108 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 109 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 110 111 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 112 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 113 114 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 115 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 116 117 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 118 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 119 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 120 121 // These are target-independent nodes, but have target-specific formats. 122 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 123 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 124 SDTCisVT<1, i32> ]>; 125 126 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 127 [SDNPHasChain, SDNPOutGlue]>; 128 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 129 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 130 131 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 132 def call : SDNode<"SPISD::CALL", SDT_SPCall, 133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 134 SDNPVariadic]>; 135 136 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 137 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 138 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 139 140 def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 141 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 142 143 def getPCX : Operand<i32> { 144 let PrintMethod = "printGetPCX"; 145 } 146 147 //===----------------------------------------------------------------------===// 148 // SPARC Flag Conditions 149 //===----------------------------------------------------------------------===// 150 151 // Note that these values must be kept in sync with the CCOp::CondCode enum 152 // values. 153 class ICC_VAL<int N> : PatLeaf<(i32 N)>; 154 def ICC_NE : ICC_VAL< 9>; // Not Equal 155 def ICC_E : ICC_VAL< 1>; // Equal 156 def ICC_G : ICC_VAL<10>; // Greater 157 def ICC_LE : ICC_VAL< 2>; // Less or Equal 158 def ICC_GE : ICC_VAL<11>; // Greater or Equal 159 def ICC_L : ICC_VAL< 3>; // Less 160 def ICC_GU : ICC_VAL<12>; // Greater Unsigned 161 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 162 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 163 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 164 def ICC_POS : ICC_VAL<14>; // Positive 165 def ICC_NEG : ICC_VAL< 6>; // Negative 166 def ICC_VC : ICC_VAL<15>; // Overflow Clear 167 def ICC_VS : ICC_VAL< 7>; // Overflow Set 168 169 class FCC_VAL<int N> : PatLeaf<(i32 N)>; 170 def FCC_U : FCC_VAL<23>; // Unordered 171 def FCC_G : FCC_VAL<22>; // Greater 172 def FCC_UG : FCC_VAL<21>; // Unordered or Greater 173 def FCC_L : FCC_VAL<20>; // Less 174 def FCC_UL : FCC_VAL<19>; // Unordered or Less 175 def FCC_LG : FCC_VAL<18>; // Less or Greater 176 def FCC_NE : FCC_VAL<17>; // Not Equal 177 def FCC_E : FCC_VAL<25>; // Equal 178 def FCC_UE : FCC_VAL<24>; // Unordered or Equal 179 def FCC_GE : FCC_VAL<25>; // Greater or Equal 180 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 181 def FCC_LE : FCC_VAL<27>; // Less or Equal 182 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 183 def FCC_O : FCC_VAL<29>; // Ordered 184 185 //===----------------------------------------------------------------------===// 186 // Instruction Class Templates 187 //===----------------------------------------------------------------------===// 188 189 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 190 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 191 def rr : F3_1<2, Op3Val, 192 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 193 !strconcat(OpcStr, " $b, $c, $dst"), 194 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; 195 def ri : F3_2<2, Op3Val, 196 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 197 !strconcat(OpcStr, " $b, $c, $dst"), 198 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>; 199 } 200 201 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 202 /// pattern. 203 multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 204 def rr : F3_1<2, Op3Val, 205 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 206 !strconcat(OpcStr, " $b, $c, $dst"), []>; 207 def ri : F3_2<2, Op3Val, 208 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 209 !strconcat(OpcStr, " $b, $c, $dst"), []>; 210 } 211 212 //===----------------------------------------------------------------------===// 213 // Instructions 214 //===----------------------------------------------------------------------===// 215 216 // Pseudo instructions. 217 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 218 : InstSP<outs, ins, asmstr, pattern>; 219 220 // GETPCX for PIC 221 let Defs = [O7] in { 222 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 223 } 224 225 let Defs = [O6], Uses = [O6] in { 226 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 227 "!ADJCALLSTACKDOWN $amt", 228 [(callseq_start timm:$amt)]>; 229 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 230 "!ADJCALLSTACKUP $amt1", 231 [(callseq_end timm:$amt1, timm:$amt2)]>; 232 } 233 234 let hasSideEffects = 1, mayStore = 1 in { 235 let rd = 0, rs1 = 0, rs2 = 0 in 236 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 237 "flushw", 238 [(flushw)]>, Requires<[HasV9]>; 239 let rd = 0, rs1 = 1, simm13 = 3 in 240 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 241 "ta 3", 242 [(flushw)]>; 243 } 244 245 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 246 "unimp $val", []>; 247 248 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 249 // instruction selection into a branch sequence. This has to handle all 250 // permutations of selection between i32/f32/f64 on ICC and FCC. 251 // Expanded after instruction selection. 252 let Uses = [ICC], usesCustomInserter = 1 in { 253 def SELECT_CC_Int_ICC 254 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 255 "; SELECT_CC_Int_ICC PSEUDO!", 256 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 257 def SELECT_CC_FP_ICC 258 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 259 "; SELECT_CC_FP_ICC PSEUDO!", 260 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 261 262 def SELECT_CC_DFP_ICC 263 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 264 "; SELECT_CC_DFP_ICC PSEUDO!", 265 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 266 } 267 268 let usesCustomInserter = 1, Uses = [FCC] in { 269 270 def SELECT_CC_Int_FCC 271 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 272 "; SELECT_CC_Int_FCC PSEUDO!", 273 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 274 275 def SELECT_CC_FP_FCC 276 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 277 "; SELECT_CC_FP_FCC PSEUDO!", 278 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 279 def SELECT_CC_DFP_FCC 280 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 281 "; SELECT_CC_DFP_FCC PSEUDO!", 282 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 283 } 284 285 286 // Section A.3 - Synthetic Instructions, p. 85 287 // special cases of JMPL: 288 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 289 let rd = O7.Num, rs1 = G0.Num in 290 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 291 "jmp %o7+$val", [(retflag simm13:$val)]>; 292 293 let rd = I7.Num, rs1 = G0.Num in 294 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 295 "jmp %i7+$val", []>; 296 } 297 298 // Section B.1 - Load Integer Instructions, p. 90 299 def LDSBrr : F3_1<3, 0b001001, 300 (outs IntRegs:$dst), (ins MEMrr:$addr), 301 "ldsb [$addr], $dst", 302 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 303 def LDSBri : F3_2<3, 0b001001, 304 (outs IntRegs:$dst), (ins MEMri:$addr), 305 "ldsb [$addr], $dst", 306 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 307 def LDSHrr : F3_1<3, 0b001010, 308 (outs IntRegs:$dst), (ins MEMrr:$addr), 309 "ldsh [$addr], $dst", 310 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 311 def LDSHri : F3_2<3, 0b001010, 312 (outs IntRegs:$dst), (ins MEMri:$addr), 313 "ldsh [$addr], $dst", 314 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 315 def LDUBrr : F3_1<3, 0b000001, 316 (outs IntRegs:$dst), (ins MEMrr:$addr), 317 "ldub [$addr], $dst", 318 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 319 def LDUBri : F3_2<3, 0b000001, 320 (outs IntRegs:$dst), (ins MEMri:$addr), 321 "ldub [$addr], $dst", 322 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 323 def LDUHrr : F3_1<3, 0b000010, 324 (outs IntRegs:$dst), (ins MEMrr:$addr), 325 "lduh [$addr], $dst", 326 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 327 def LDUHri : F3_2<3, 0b000010, 328 (outs IntRegs:$dst), (ins MEMri:$addr), 329 "lduh [$addr], $dst", 330 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 331 def LDrr : F3_1<3, 0b000000, 332 (outs IntRegs:$dst), (ins MEMrr:$addr), 333 "ld [$addr], $dst", 334 [(set i32:$dst, (load ADDRrr:$addr))]>; 335 def LDri : F3_2<3, 0b000000, 336 (outs IntRegs:$dst), (ins MEMri:$addr), 337 "ld [$addr], $dst", 338 [(set i32:$dst, (load ADDRri:$addr))]>; 339 340 // Section B.2 - Load Floating-point Instructions, p. 92 341 def LDFrr : F3_1<3, 0b100000, 342 (outs FPRegs:$dst), (ins MEMrr:$addr), 343 "ld [$addr], $dst", 344 [(set f32:$dst, (load ADDRrr:$addr))]>; 345 def LDFri : F3_2<3, 0b100000, 346 (outs FPRegs:$dst), (ins MEMri:$addr), 347 "ld [$addr], $dst", 348 [(set f32:$dst, (load ADDRri:$addr))]>; 349 def LDDFrr : F3_1<3, 0b100011, 350 (outs DFPRegs:$dst), (ins MEMrr:$addr), 351 "ldd [$addr], $dst", 352 [(set f64:$dst, (load ADDRrr:$addr))]>; 353 def LDDFri : F3_2<3, 0b100011, 354 (outs DFPRegs:$dst), (ins MEMri:$addr), 355 "ldd [$addr], $dst", 356 [(set f64:$dst, (load ADDRri:$addr))]>; 357 358 // Section B.4 - Store Integer Instructions, p. 95 359 def STBrr : F3_1<3, 0b000101, 360 (outs), (ins MEMrr:$addr, IntRegs:$src), 361 "stb $src, [$addr]", 362 [(truncstorei8 i32:$src, ADDRrr:$addr)]>; 363 def STBri : F3_2<3, 0b000101, 364 (outs), (ins MEMri:$addr, IntRegs:$src), 365 "stb $src, [$addr]", 366 [(truncstorei8 i32:$src, ADDRri:$addr)]>; 367 def STHrr : F3_1<3, 0b000110, 368 (outs), (ins MEMrr:$addr, IntRegs:$src), 369 "sth $src, [$addr]", 370 [(truncstorei16 i32:$src, ADDRrr:$addr)]>; 371 def STHri : F3_2<3, 0b000110, 372 (outs), (ins MEMri:$addr, IntRegs:$src), 373 "sth $src, [$addr]", 374 [(truncstorei16 i32:$src, ADDRri:$addr)]>; 375 def STrr : F3_1<3, 0b000100, 376 (outs), (ins MEMrr:$addr, IntRegs:$src), 377 "st $src, [$addr]", 378 [(store i32:$src, ADDRrr:$addr)]>; 379 def STri : F3_2<3, 0b000100, 380 (outs), (ins MEMri:$addr, IntRegs:$src), 381 "st $src, [$addr]", 382 [(store i32:$src, ADDRri:$addr)]>; 383 384 // Section B.5 - Store Floating-point Instructions, p. 97 385 def STFrr : F3_1<3, 0b100100, 386 (outs), (ins MEMrr:$addr, FPRegs:$src), 387 "st $src, [$addr]", 388 [(store f32:$src, ADDRrr:$addr)]>; 389 def STFri : F3_2<3, 0b100100, 390 (outs), (ins MEMri:$addr, FPRegs:$src), 391 "st $src, [$addr]", 392 [(store f32:$src, ADDRri:$addr)]>; 393 def STDFrr : F3_1<3, 0b100111, 394 (outs), (ins MEMrr:$addr, DFPRegs:$src), 395 "std $src, [$addr]", 396 [(store f64:$src, ADDRrr:$addr)]>; 397 def STDFri : F3_2<3, 0b100111, 398 (outs), (ins MEMri:$addr, DFPRegs:$src), 399 "std $src, [$addr]", 400 [(store f64:$src, ADDRri:$addr)]>; 401 402 // Section B.9 - SETHI Instruction, p. 104 403 def SETHIi: F2_1<0b100, 404 (outs IntRegs:$dst), (ins i32imm:$src), 405 "sethi $src, $dst", 406 [(set i32:$dst, SETHIimm:$src)]>; 407 408 // Section B.10 - NOP Instruction, p. 105 409 // (It's a special case of SETHI) 410 let rd = 0, imm22 = 0 in 411 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 412 413 // Section B.11 - Logical Instructions, p. 106 414 defm AND : F3_12<"and", 0b000001, and>; 415 416 def ANDNrr : F3_1<2, 0b000101, 417 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 418 "andn $b, $c, $dst", 419 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 420 def ANDNri : F3_2<2, 0b000101, 421 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 422 "andn $b, $c, $dst", []>; 423 424 defm OR : F3_12<"or", 0b000010, or>; 425 426 def ORNrr : F3_1<2, 0b000110, 427 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 428 "orn $b, $c, $dst", 429 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 430 def ORNri : F3_2<2, 0b000110, 431 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 432 "orn $b, $c, $dst", []>; 433 defm XOR : F3_12<"xor", 0b000011, xor>; 434 435 def XNORrr : F3_1<2, 0b000111, 436 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 437 "xnor $b, $c, $dst", 438 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 439 def XNORri : F3_2<2, 0b000111, 440 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 441 "xnor $b, $c, $dst", []>; 442 443 // Section B.12 - Shift Instructions, p. 107 444 defm SLL : F3_12<"sll", 0b100101, shl>; 445 defm SRL : F3_12<"srl", 0b100110, srl>; 446 defm SRA : F3_12<"sra", 0b100111, sra>; 447 448 // Section B.13 - Add Instructions, p. 108 449 defm ADD : F3_12<"add", 0b000000, add>; 450 451 // "LEA" forms of add (patterns to make tblgen happy) 452 def LEA_ADDri : F3_2<2, 0b000000, 453 (outs IntRegs:$dst), (ins MEMri:$addr), 454 "add ${addr:arith}, $dst", 455 [(set iPTR:$dst, ADDRri:$addr)]>; 456 457 let Defs = [ICC] in 458 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 459 460 let Uses = [ICC] in 461 defm ADDX : F3_12<"addx", 0b001000, adde>; 462 463 // Section B.15 - Subtract Instructions, p. 110 464 defm SUB : F3_12 <"sub" , 0b000100, sub>; 465 let Uses = [ICC] in 466 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 467 468 let Defs = [ICC] in { 469 defm SUBCC : F3_12 <"subcc", 0b010100, subc>; 470 471 def CMPrr : F3_1<2, 0b010100, 472 (outs), (ins IntRegs:$b, IntRegs:$c), 473 "cmp $b, $c", 474 [(SPcmpicc i32:$b, i32:$c)]>; 475 def CMPri : F3_1<2, 0b010100, 476 (outs), (ins IntRegs:$b, i32imm:$c), 477 "cmp $b, $c", 478 [(SPcmpicc i32:$b, (i32 simm13:$c))]>; 479 } 480 481 let Uses = [ICC], Defs = [ICC] in 482 def SUBXCCrr: F3_1<2, 0b011100, 483 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 484 "subxcc $b, $c, $dst", []>; 485 486 487 // Section B.18 - Multiply Instructions, p. 113 488 let Defs = [Y] in { 489 defm UMUL : F3_12np<"umul", 0b001010>; 490 defm SMUL : F3_12 <"smul", 0b001011, mul>; 491 } 492 493 // Section B.19 - Divide Instructions, p. 115 494 let Defs = [Y] in { 495 defm UDIV : F3_12np<"udiv", 0b001110>; 496 defm SDIV : F3_12np<"sdiv", 0b001111>; 497 } 498 499 // Section B.20 - SAVE and RESTORE, p. 117 500 defm SAVE : F3_12np<"save" , 0b111100>; 501 defm RESTORE : F3_12np<"restore", 0b111101>; 502 503 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 504 505 // conditional branch class: 506 class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 507 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 508 let isBranch = 1; 509 let isTerminator = 1; 510 let hasDelaySlot = 1; 511 } 512 513 let isBarrier = 1 in 514 def BA : BranchSP<0b1000, (ins brtarget:$dst), 515 "ba $dst", 516 [(br bb:$dst)]>; 517 518 // Indirect branch instructions. 519 let isTerminator = 1, isBarrier = 1, 520 hasDelaySlot = 1, isBranch =1, 521 isIndirectBranch = 1 in { 522 def BINDrr : F3_1<2, 0b111000, 523 (outs), (ins MEMrr:$ptr), 524 "jmp $ptr", 525 [(brind ADDRrr:$ptr)]>; 526 def BINDri : F3_2<2, 0b111000, 527 (outs), (ins MEMri:$ptr), 528 "jmp $ptr", 529 [(brind ADDRri:$ptr)]>; 530 } 531 532 // FIXME: the encoding for the JIT should look at the condition field. 533 let Uses = [ICC] in 534 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 535 "b$cc $dst", 536 [(SPbricc bb:$dst, imm:$cc)]>; 537 538 539 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 540 541 // floating-point conditional branch class: 542 class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 543 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 544 let isBranch = 1; 545 let isTerminator = 1; 546 let hasDelaySlot = 1; 547 } 548 549 // FIXME: the encoding for the JIT should look at the condition field. 550 let Uses = [FCC] in 551 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 552 "fb$cc $dst", 553 [(SPbrfcc bb:$dst, imm:$cc)]>; 554 555 556 // Section B.24 - Call and Link Instruction, p. 125 557 // This is the only Format 1 instruction 558 let Uses = [O6], 559 hasDelaySlot = 1, isCall = 1, 560 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 561 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 562 ICC, FCC, Y] in { 563 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 564 "call $dst", []> { 565 bits<30> disp; 566 let op = 1; 567 let Inst{29-0} = disp; 568 } 569 570 // indirect calls 571 def JMPLrr : F3_1<2, 0b111000, 572 (outs), (ins MEMrr:$ptr, variable_ops), 573 "call $ptr", 574 [(call ADDRrr:$ptr)]>; 575 def JMPLri : F3_2<2, 0b111000, 576 (outs), (ins MEMri:$ptr, variable_ops), 577 "call $ptr", 578 [(call ADDRri:$ptr)]>; 579 } 580 581 // Section B.28 - Read State Register Instructions 582 let Uses = [Y] in 583 def RDY : F3_1<2, 0b101000, 584 (outs IntRegs:$dst), (ins), 585 "rd %y, $dst", []>; 586 587 // Section B.29 - Write State Register Instructions 588 let Defs = [Y] in { 589 def WRYrr : F3_1<2, 0b110000, 590 (outs), (ins IntRegs:$b, IntRegs:$c), 591 "wr $b, $c, %y", []>; 592 def WRYri : F3_2<2, 0b110000, 593 (outs), (ins IntRegs:$b, i32imm:$c), 594 "wr $b, $c, %y", []>; 595 } 596 // Convert Integer to Floating-point Instructions, p. 141 597 def FITOS : F3_3<2, 0b110100, 0b011000100, 598 (outs FPRegs:$dst), (ins FPRegs:$src), 599 "fitos $src, $dst", 600 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 601 def FITOD : F3_3<2, 0b110100, 0b011001000, 602 (outs DFPRegs:$dst), (ins FPRegs:$src), 603 "fitod $src, $dst", 604 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 605 606 // Convert Floating-point to Integer Instructions, p. 142 607 def FSTOI : F3_3<2, 0b110100, 0b011010001, 608 (outs FPRegs:$dst), (ins FPRegs:$src), 609 "fstoi $src, $dst", 610 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 611 def FDTOI : F3_3<2, 0b110100, 0b011010010, 612 (outs FPRegs:$dst), (ins DFPRegs:$src), 613 "fdtoi $src, $dst", 614 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 615 616 // Convert between Floating-point Formats Instructions, p. 143 617 def FSTOD : F3_3<2, 0b110100, 0b011001001, 618 (outs DFPRegs:$dst), (ins FPRegs:$src), 619 "fstod $src, $dst", 620 [(set f64:$dst, (fextend f32:$src))]>; 621 def FDTOS : F3_3<2, 0b110100, 0b011000110, 622 (outs FPRegs:$dst), (ins DFPRegs:$src), 623 "fdtos $src, $dst", 624 [(set f32:$dst, (fround f64:$src))]>; 625 626 // Floating-point Move Instructions, p. 144 627 def FMOVS : F3_3<2, 0b110100, 0b000000001, 628 (outs FPRegs:$dst), (ins FPRegs:$src), 629 "fmovs $src, $dst", []>; 630 def FNEGS : F3_3<2, 0b110100, 0b000000101, 631 (outs FPRegs:$dst), (ins FPRegs:$src), 632 "fnegs $src, $dst", 633 [(set f32:$dst, (fneg f32:$src))]>; 634 def FABSS : F3_3<2, 0b110100, 0b000001001, 635 (outs FPRegs:$dst), (ins FPRegs:$src), 636 "fabss $src, $dst", 637 [(set f32:$dst, (fabs f32:$src))]>; 638 639 640 // Floating-point Square Root Instructions, p.145 641 def FSQRTS : F3_3<2, 0b110100, 0b000101001, 642 (outs FPRegs:$dst), (ins FPRegs:$src), 643 "fsqrts $src, $dst", 644 [(set f32:$dst, (fsqrt f32:$src))]>; 645 def FSQRTD : F3_3<2, 0b110100, 0b000101010, 646 (outs DFPRegs:$dst), (ins DFPRegs:$src), 647 "fsqrtd $src, $dst", 648 [(set f64:$dst, (fsqrt f64:$src))]>; 649 650 651 652 // Floating-point Add and Subtract Instructions, p. 146 653 def FADDS : F3_3<2, 0b110100, 0b001000001, 654 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 655 "fadds $src1, $src2, $dst", 656 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 657 def FADDD : F3_3<2, 0b110100, 0b001000010, 658 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 659 "faddd $src1, $src2, $dst", 660 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 661 def FSUBS : F3_3<2, 0b110100, 0b001000101, 662 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 663 "fsubs $src1, $src2, $dst", 664 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 665 def FSUBD : F3_3<2, 0b110100, 0b001000110, 666 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 667 "fsubd $src1, $src2, $dst", 668 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 669 670 // Floating-point Multiply and Divide Instructions, p. 147 671 def FMULS : F3_3<2, 0b110100, 0b001001001, 672 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 673 "fmuls $src1, $src2, $dst", 674 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 675 def FMULD : F3_3<2, 0b110100, 0b001001010, 676 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 677 "fmuld $src1, $src2, $dst", 678 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 679 def FSMULD : F3_3<2, 0b110100, 0b001101001, 680 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 681 "fsmuld $src1, $src2, $dst", 682 [(set f64:$dst, (fmul (fextend f32:$src1), 683 (fextend f32:$src2)))]>; 684 def FDIVS : F3_3<2, 0b110100, 0b001001101, 685 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 686 "fdivs $src1, $src2, $dst", 687 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 688 def FDIVD : F3_3<2, 0b110100, 0b001001110, 689 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 690 "fdivd $src1, $src2, $dst", 691 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 692 693 // Floating-point Compare Instructions, p. 148 694 // Note: the 2nd template arg is different for these guys. 695 // Note 2: the result of a FCMP is not available until the 2nd cycle 696 // after the instr is retired, but there is no interlock. This behavior 697 // is modelled with a forced noop after the instruction. 698 let Defs = [FCC] in { 699 def FCMPS : F3_3<2, 0b110101, 0b001010001, 700 (outs), (ins FPRegs:$src1, FPRegs:$src2), 701 "fcmps $src1, $src2\n\tnop", 702 [(SPcmpfcc f32:$src1, f32:$src2)]>; 703 def FCMPD : F3_3<2, 0b110101, 0b001010010, 704 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 705 "fcmpd $src1, $src2\n\tnop", 706 [(SPcmpfcc f64:$src1, f64:$src2)]>; 707 } 708 709 //===----------------------------------------------------------------------===// 710 // V9 Instructions 711 //===----------------------------------------------------------------------===// 712 713 // V9 Conditional Moves. 714 let Predicates = [HasV9], Constraints = "$f = $rd" in { 715 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 716 // FIXME: Add instruction encodings for the JIT some day. 717 let Uses = [ICC] in { 718 def MOVICCrr 719 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 720 "mov$cc %icc, $rs2, $rd", 721 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>; 722 def MOVICCri 723 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 724 "mov$cc %icc, $i, $rd", 725 [(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>; 726 } 727 728 let Uses = [FCC] in { 729 def MOVFCCrr 730 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 731 "mov$cc %fcc0, $rs2, $rd", 732 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>; 733 def MOVFCCri 734 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 735 "mov$cc %fcc0, $i, $rd", 736 [(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>; 737 } 738 739 let Uses = [ICC] in { 740 def FMOVS_ICC 741 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 742 "fmovs$cc %icc, $rs2, $rd", 743 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>; 744 def FMOVD_ICC 745 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 746 "fmovd$cc %icc, $rs2, $rd", 747 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>; 748 } 749 750 let Uses = [FCC] in { 751 def FMOVS_FCC 752 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 753 "fmovs$cc %fcc0, $rs2, $rd", 754 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>; 755 def FMOVD_FCC 756 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 757 "fmovd$cc %fcc0, $rs2, $rd", 758 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>; 759 } 760 761 } 762 763 // Floating-Point Move Instructions, p. 164 of the V9 manual. 764 let Predicates = [HasV9] in { 765 def FMOVD : F3_3<2, 0b110100, 0b000000010, 766 (outs DFPRegs:$dst), (ins DFPRegs:$src), 767 "fmovd $src, $dst", []>; 768 def FNEGD : F3_3<2, 0b110100, 0b000000110, 769 (outs DFPRegs:$dst), (ins DFPRegs:$src), 770 "fnegd $src, $dst", 771 [(set f64:$dst, (fneg f64:$src))]>; 772 def FABSD : F3_3<2, 0b110100, 0b000001010, 773 (outs DFPRegs:$dst), (ins DFPRegs:$src), 774 "fabsd $src, $dst", 775 [(set f64:$dst, (fabs f64:$src))]>; 776 } 777 778 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 779 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 780 def POPCrr : F3_1<2, 0b101110, 781 (outs IntRegs:$dst), (ins IntRegs:$src), 782 "popc $src, $dst", []>, Requires<[HasV9]>; 783 def : Pat<(ctpop i32:$src), 784 (POPCrr (SLLri $src, 0))>; 785 786 //===----------------------------------------------------------------------===// 787 // Non-Instruction Patterns 788 //===----------------------------------------------------------------------===// 789 790 // Small immediates. 791 def : Pat<(i32 simm13:$val), 792 (ORri (i32 G0), imm:$val)>; 793 // Arbitrary immediates. 794 def : Pat<(i32 imm:$val), 795 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 796 797 798 // Global addresses, constant pool entries 799 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 800 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 801 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 802 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 803 804 // Blockaddress 805 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 806 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 807 808 // Add reg, lo. This is used when taking the addr of a global/constpool entry. 809 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 810 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 811 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 812 (ADDri $r, tblockaddress:$in)>; 813 814 // Calls: 815 def : Pat<(call tglobaladdr:$dst), 816 (CALL tglobaladdr:$dst)>; 817 def : Pat<(call texternalsym:$dst), 818 (CALL texternalsym:$dst)>; 819 820 // Map integer extload's to zextloads. 821 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 822 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 823 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 824 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 825 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 826 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 827 828 // zextload bool -> zextload byte 829 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 830 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 831 832 // store 0, addr -> store %g0, addr 833 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 834 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 835 836 include "SparcInstr64Bit.td" 837
