1 //===-- X86InstrArithmetic.td - Integer Arithmetic Instrs --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the integer arithmetic instructions in the X86 11 // architecture. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // LEA - Load Effective Address 17 let SchedRW = [WriteLEA] in { 18 let neverHasSideEffects = 1 in 19 def LEA16r : I<0x8D, MRMSrcMem, 20 (outs GR16:$dst), (ins i32mem:$src), 21 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize; 22 let isReMaterializable = 1 in 23 def LEA32r : I<0x8D, MRMSrcMem, 24 (outs GR32:$dst), (ins i32mem:$src), 25 "lea{l}\t{$src|$dst}, {$dst|$src}", 26 [(set GR32:$dst, lea32addr:$src)], IIC_LEA>, 27 Requires<[In32BitMode]>; 28 29 def LEA64_32r : I<0x8D, MRMSrcMem, 30 (outs GR32:$dst), (ins lea64_32mem:$src), 31 "lea{l}\t{$src|$dst}, {$dst|$src}", 32 [(set GR32:$dst, lea64_32addr:$src)], IIC_LEA>, 33 Requires<[In64BitMode]>; 34 35 let isReMaterializable = 1 in 36 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), 37 "lea{q}\t{$src|$dst}, {$dst|$src}", 38 [(set GR64:$dst, lea64addr:$src)], IIC_LEA>; 39 } // SchedRW 40 41 //===----------------------------------------------------------------------===// 42 // Fixed-Register Multiplication and Division Instructions. 43 // 44 45 // SchedModel info for instruction that loads one value and gets the second 46 // (and possibly third) value from a register. 47 // This is used for instructions that put the memory operands before other 48 // uses. 49 class SchedLoadReg<SchedWrite SW> : Sched<[SW, 50 // Memory operand. 51 ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, 52 // Register reads (implicit or explicit). 53 ReadAfterLd, ReadAfterLd]>; 54 55 // Extra precision multiplication 56 57 // AL is really implied by AX, but the registers in Defs must match the 58 // SDNode results (i8, i32). 59 // AL,AH = AL*GR8 60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in 61 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", 62 // FIXME: Used for 8-bit mul, ignore result upper 8 bits. 63 // This probably ought to be moved to a def : Pat<> if the 64 // syntax can be accepted. 65 [(set AL, (mul AL, GR8:$src)), 66 (implicit EFLAGS)], IIC_MUL8>, Sched<[WriteIMul]>; 67 // AX,DX = AX*GR16 68 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in 69 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), 70 "mul{w}\t$src", 71 [], IIC_MUL16_REG>, OpSize, Sched<[WriteIMul]>; 72 // EAX,EDX = EAX*GR32 73 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in 74 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), 75 "mul{l}\t$src", 76 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/], 77 IIC_MUL32_REG>, Sched<[WriteIMul]>; 78 // RAX,RDX = RAX*GR64 79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in 80 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src), 81 "mul{q}\t$src", 82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/], 83 IIC_MUL64>, Sched<[WriteIMul]>; 84 // AL,AH = AL*[mem8] 85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in 86 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), 87 "mul{b}\t$src", 88 // FIXME: Used for 8-bit mul, ignore result upper 8 bits. 89 // This probably ought to be moved to a def : Pat<> if the 90 // syntax can be accepted. 91 [(set AL, (mul AL, (loadi8 addr:$src))), 92 (implicit EFLAGS)], IIC_MUL8>, SchedLoadReg<WriteIMulLd>; 93 // AX,DX = AX*[mem16] 94 let mayLoad = 1, neverHasSideEffects = 1 in { 95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in 96 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), 97 "mul{w}\t$src", 98 [], IIC_MUL16_MEM>, OpSize, SchedLoadReg<WriteIMulLd>; 99 // EAX,EDX = EAX*[mem32] 100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in 101 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), 102 "mul{l}\t$src", 103 [], IIC_MUL32_MEM>, SchedLoadReg<WriteIMulLd>; 104 // RAX,RDX = RAX*[mem64] 105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in 106 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src), 107 "mul{q}\t$src", [], IIC_MUL64>, SchedLoadReg<WriteIMulLd>; 108 } 109 110 let neverHasSideEffects = 1 in { 111 // AL,AH = AL*GR8 112 let Defs = [AL,EFLAGS,AX], Uses = [AL] in 113 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [], 114 IIC_IMUL8>, Sched<[WriteIMul]>; 115 // AX,DX = AX*GR16 116 let Defs = [AX,DX,EFLAGS], Uses = [AX] in 117 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [], 118 IIC_IMUL16_RR>, OpSize, Sched<[WriteIMul]>; 119 // EAX,EDX = EAX*GR32 120 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in 121 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [], 122 IIC_IMUL32_RR>, Sched<[WriteIMul]>; 123 // RAX,RDX = RAX*GR64 124 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in 125 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [], 126 IIC_IMUL64_RR>, Sched<[WriteIMul]>; 127 128 let mayLoad = 1 in { 129 // AL,AH = AL*[mem8] 130 let Defs = [AL,EFLAGS,AX], Uses = [AL] in 131 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), 132 "imul{b}\t$src", [], IIC_IMUL8>, SchedLoadReg<WriteIMulLd>; 133 // AX,DX = AX*[mem16] 134 let Defs = [AX,DX,EFLAGS], Uses = [AX] in 135 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), 136 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize, 137 SchedLoadReg<WriteIMulLd>; 138 // EAX,EDX = EAX*[mem32] 139 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in 140 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), 141 "imul{l}\t$src", [], IIC_IMUL32_MEM>, SchedLoadReg<WriteIMulLd>; 142 // RAX,RDX = RAX*[mem64] 143 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in 144 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src), 145 "imul{q}\t$src", [], IIC_IMUL64>, SchedLoadReg<WriteIMulLd>; 146 } 147 } // neverHasSideEffects 148 149 150 let Defs = [EFLAGS] in { 151 let Constraints = "$src1 = $dst" in { 152 153 let isCommutable = 1, SchedRW = [WriteIMul] in { 154 // X = IMUL Y, Z --> X = IMUL Z, Y 155 // Register-Register Signed Integer Multiply 156 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), 157 "imul{w}\t{$src2, $dst|$dst, $src2}", 158 [(set GR16:$dst, EFLAGS, 159 (X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>, 160 TB, OpSize; 161 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), 162 "imul{l}\t{$src2, $dst|$dst, $src2}", 163 [(set GR32:$dst, EFLAGS, 164 (X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>, 165 TB; 166 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), 167 (ins GR64:$src1, GR64:$src2), 168 "imul{q}\t{$src2, $dst|$dst, $src2}", 169 [(set GR64:$dst, EFLAGS, 170 (X86smul_flag GR64:$src1, GR64:$src2))], IIC_IMUL64_RR>, 171 TB; 172 } // isCommutable, SchedRW 173 174 // Register-Memory Signed Integer Multiply 175 let SchedRW = [WriteIMulLd, ReadAfterLd] in { 176 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), 177 (ins GR16:$src1, i16mem:$src2), 178 "imul{w}\t{$src2, $dst|$dst, $src2}", 179 [(set GR16:$dst, EFLAGS, 180 (X86smul_flag GR16:$src1, (load addr:$src2)))], 181 IIC_IMUL16_RM>, 182 TB, OpSize; 183 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), 184 (ins GR32:$src1, i32mem:$src2), 185 "imul{l}\t{$src2, $dst|$dst, $src2}", 186 [(set GR32:$dst, EFLAGS, 187 (X86smul_flag GR32:$src1, (load addr:$src2)))], 188 IIC_IMUL32_RM>, 189 TB; 190 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), 191 (ins GR64:$src1, i64mem:$src2), 192 "imul{q}\t{$src2, $dst|$dst, $src2}", 193 [(set GR64:$dst, EFLAGS, 194 (X86smul_flag GR64:$src1, (load addr:$src2)))], 195 IIC_IMUL64_RM>, 196 TB; 197 } // SchedRW 198 } // Constraints = "$src1 = $dst" 199 200 } // Defs = [EFLAGS] 201 202 // Surprisingly enough, these are not two address instructions! 203 let Defs = [EFLAGS] in { 204 let SchedRW = [WriteIMul] in { 205 // Register-Integer Signed Integer Multiply 206 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 207 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 208 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 209 [(set GR16:$dst, EFLAGS, 210 (X86smul_flag GR16:$src1, imm:$src2))], 211 IIC_IMUL16_RRI>, OpSize; 212 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 213 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 214 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 215 [(set GR16:$dst, EFLAGS, 216 (X86smul_flag GR16:$src1, i16immSExt8:$src2))], 217 IIC_IMUL16_RRI>, 218 OpSize; 219 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 220 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 222 [(set GR32:$dst, EFLAGS, 223 (X86smul_flag GR32:$src1, imm:$src2))], 224 IIC_IMUL32_RRI>; 225 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 226 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 227 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 228 [(set GR32:$dst, EFLAGS, 229 (X86smul_flag GR32:$src1, i32immSExt8:$src2))], 230 IIC_IMUL32_RRI>; 231 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32 232 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 234 [(set GR64:$dst, EFLAGS, 235 (X86smul_flag GR64:$src1, i64immSExt32:$src2))], 236 IIC_IMUL64_RRI>; 237 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8 238 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 239 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 240 [(set GR64:$dst, EFLAGS, 241 (X86smul_flag GR64:$src1, i64immSExt8:$src2))], 242 IIC_IMUL64_RRI>; 243 } // SchedRW 244 245 // Memory-Integer Signed Integer Multiply 246 let SchedRW = [WriteIMulLd] in { 247 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 248 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), 249 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 250 [(set GR16:$dst, EFLAGS, 251 (X86smul_flag (load addr:$src1), imm:$src2))], 252 IIC_IMUL16_RMI>, 253 OpSize; 254 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 255 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), 256 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 257 [(set GR16:$dst, EFLAGS, 258 (X86smul_flag (load addr:$src1), 259 i16immSExt8:$src2))], IIC_IMUL16_RMI>, 260 OpSize; 261 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 262 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), 263 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 264 [(set GR32:$dst, EFLAGS, 265 (X86smul_flag (load addr:$src1), imm:$src2))], 266 IIC_IMUL32_RMI>; 267 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 268 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), 269 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 270 [(set GR32:$dst, EFLAGS, 271 (X86smul_flag (load addr:$src1), 272 i32immSExt8:$src2))], 273 IIC_IMUL32_RMI>; 274 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32 275 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2), 276 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 277 [(set GR64:$dst, EFLAGS, 278 (X86smul_flag (load addr:$src1), 279 i64immSExt32:$src2))], 280 IIC_IMUL64_RMI>; 281 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8 282 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2), 283 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 284 [(set GR64:$dst, EFLAGS, 285 (X86smul_flag (load addr:$src1), 286 i64immSExt8:$src2))], 287 IIC_IMUL64_RMI>; 288 } // SchedRW 289 } // Defs = [EFLAGS] 290 291 292 293 294 // unsigned division/remainder 295 let hasSideEffects = 1 in { // so that we don't speculatively execute 296 let SchedRW = [WriteIDiv] in { 297 let Defs = [AL,AH,EFLAGS], Uses = [AX] in 298 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH 299 "div{b}\t$src", [], IIC_DIV8_REG>; 300 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in 301 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX 302 "div{w}\t$src", [], IIC_DIV16>, OpSize; 303 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in 304 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX 305 "div{l}\t$src", [], IIC_DIV32>; 306 // RDX:RAX/r64 = RAX,RDX 307 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in 308 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), 309 "div{q}\t$src", [], IIC_DIV64>; 310 } // SchedRW 311 312 let mayLoad = 1 in { 313 let Defs = [AL,AH,EFLAGS], Uses = [AX] in 314 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH 315 "div{b}\t$src", [], IIC_DIV8_MEM>, 316 SchedLoadReg<WriteIDivLd>; 317 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in 318 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX 319 "div{w}\t$src", [], IIC_DIV16>, OpSize, 320 SchedLoadReg<WriteIDivLd>; 321 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX 322 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), 323 "div{l}\t$src", [], IIC_DIV32>, 324 SchedLoadReg<WriteIDivLd>; 325 // RDX:RAX/[mem64] = RAX,RDX 326 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in 327 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), 328 "div{q}\t$src", [], IIC_DIV64>, 329 SchedLoadReg<WriteIDivLd>; 330 } 331 332 // Signed division/remainder. 333 let SchedRW = [WriteIDiv] in { 334 let Defs = [AL,AH,EFLAGS], Uses = [AX] in 335 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH 336 "idiv{b}\t$src", [], IIC_IDIV8>; 337 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in 338 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX 339 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize; 340 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in 341 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX 342 "idiv{l}\t$src", [], IIC_IDIV32>; 343 // RDX:RAX/r64 = RAX,RDX 344 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in 345 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), 346 "idiv{q}\t$src", [], IIC_IDIV64>; 347 } // SchedRW 348 349 let mayLoad = 1 in { 350 let Defs = [AL,AH,EFLAGS], Uses = [AX] in 351 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH 352 "idiv{b}\t$src", [], IIC_IDIV8>, 353 SchedLoadReg<WriteIDivLd>; 354 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in 355 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX 356 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize, 357 SchedLoadReg<WriteIDivLd>; 358 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX 359 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), 360 "idiv{l}\t$src", [], IIC_IDIV32>, 361 SchedLoadReg<WriteIDivLd>; 362 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX 363 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), 364 "idiv{q}\t$src", [], IIC_IDIV64>, 365 SchedLoadReg<WriteIDivLd>; 366 } 367 } // hasSideEffects = 0 368 369 //===----------------------------------------------------------------------===// 370 // Two address Instructions. 371 // 372 373 // unary instructions 374 let CodeSize = 2 in { 375 let Defs = [EFLAGS] in { 376 let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { 377 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1), 378 "neg{b}\t$dst", 379 [(set GR8:$dst, (ineg GR8:$src1)), 380 (implicit EFLAGS)], IIC_UNARY_REG>; 381 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1), 382 "neg{w}\t$dst", 383 [(set GR16:$dst, (ineg GR16:$src1)), 384 (implicit EFLAGS)], IIC_UNARY_REG>, OpSize; 385 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1), 386 "neg{l}\t$dst", 387 [(set GR32:$dst, (ineg GR32:$src1)), 388 (implicit EFLAGS)], IIC_UNARY_REG>; 389 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst", 390 [(set GR64:$dst, (ineg GR64:$src1)), 391 (implicit EFLAGS)], IIC_UNARY_REG>; 392 } // Constraints = "$src1 = $dst", SchedRW 393 394 // Read-modify-write negate. 395 let SchedRW = [WriteALULd, WriteRMW] in { 396 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), 397 "neg{b}\t$dst", 398 [(store (ineg (loadi8 addr:$dst)), addr:$dst), 399 (implicit EFLAGS)], IIC_UNARY_MEM>; 400 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), 401 "neg{w}\t$dst", 402 [(store (ineg (loadi16 addr:$dst)), addr:$dst), 403 (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize; 404 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), 405 "neg{l}\t$dst", 406 [(store (ineg (loadi32 addr:$dst)), addr:$dst), 407 (implicit EFLAGS)], IIC_UNARY_MEM>; 408 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst", 409 [(store (ineg (loadi64 addr:$dst)), addr:$dst), 410 (implicit EFLAGS)], IIC_UNARY_MEM>; 411 } // SchedRW 412 } // Defs = [EFLAGS] 413 414 415 // Note: NOT does not set EFLAGS! 416 417 let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { 418 // Match xor -1 to not. Favors these over a move imm + xor to save code size. 419 let AddedComplexity = 15 in { 420 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1), 421 "not{b}\t$dst", 422 [(set GR8:$dst, (not GR8:$src1))], IIC_UNARY_REG>; 423 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1), 424 "not{w}\t$dst", 425 [(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize; 426 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1), 427 "not{l}\t$dst", 428 [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>; 429 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst", 430 [(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>; 431 } 432 } // Constraints = "$src1 = $dst", SchedRW 433 434 let SchedRW = [WriteALULd, WriteRMW] in { 435 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), 436 "not{b}\t$dst", 437 [(store (not (loadi8 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>; 438 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), 439 "not{w}\t$dst", 440 [(store (not (loadi16 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>, 441 OpSize; 442 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), 443 "not{l}\t$dst", 444 [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>; 445 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst", 446 [(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>; 447 } // SchedRW 448 } // CodeSize 449 450 // TODO: inc/dec is slow for P4, but fast for Pentium-M. 451 let Defs = [EFLAGS] in { 452 let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { 453 let CodeSize = 2 in 454 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), 455 "inc{b}\t$dst", 456 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))], 457 IIC_UNARY_REG>; 458 459 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. 460 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), 461 "inc{w}\t$dst", 462 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], IIC_UNARY_REG>, 463 OpSize, Requires<[In32BitMode]>; 464 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), 465 "inc{l}\t$dst", 466 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))], 467 IIC_UNARY_REG>, 468 Requires<[In32BitMode]>; 469 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst", 470 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))], 471 IIC_UNARY_REG>; 472 } // isConvertibleToThreeAddress = 1, CodeSize = 1 473 474 475 // In 64-bit mode, single byte INC and DEC cannot be encoded. 476 let isConvertibleToThreeAddress = 1, CodeSize = 2 in { 477 // Can transform into LEA. 478 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1), 479 "inc{w}\t$dst", 480 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], 481 IIC_UNARY_REG>, 482 OpSize, Requires<[In64BitMode]>; 483 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1), 484 "inc{l}\t$dst", 485 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))], 486 IIC_UNARY_REG>, 487 Requires<[In64BitMode]>; 488 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 489 "dec{w}\t$dst", 490 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))], 491 IIC_UNARY_REG>, 492 OpSize, Requires<[In64BitMode]>; 493 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 494 "dec{l}\t$dst", 495 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))], 496 IIC_UNARY_REG>, 497 Requires<[In64BitMode]>; 498 } // isConvertibleToThreeAddress = 1, CodeSize = 2 499 500 } // Constraints = "$src1 = $dst", SchedRW 501 502 let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in { 503 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", 504 [(store (add (loadi8 addr:$dst), 1), addr:$dst), 505 (implicit EFLAGS)], IIC_UNARY_MEM>; 506 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", 507 [(store (add (loadi16 addr:$dst), 1), addr:$dst), 508 (implicit EFLAGS)], IIC_UNARY_MEM>, 509 OpSize, Requires<[In32BitMode]>; 510 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", 511 [(store (add (loadi32 addr:$dst), 1), addr:$dst), 512 (implicit EFLAGS)], IIC_UNARY_MEM>, 513 Requires<[In32BitMode]>; 514 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst", 515 [(store (add (loadi64 addr:$dst), 1), addr:$dst), 516 (implicit EFLAGS)], IIC_UNARY_MEM>; 517 518 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows 519 // how to unfold them. 520 // FIXME: What is this for?? 521 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", 522 [(store (add (loadi16 addr:$dst), 1), addr:$dst), 523 (implicit EFLAGS)], IIC_UNARY_MEM>, 524 OpSize, Requires<[In64BitMode]>; 525 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", 526 [(store (add (loadi32 addr:$dst), 1), addr:$dst), 527 (implicit EFLAGS)], IIC_UNARY_MEM>, 528 Requires<[In64BitMode]>; 529 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", 530 [(store (add (loadi16 addr:$dst), -1), addr:$dst), 531 (implicit EFLAGS)], IIC_UNARY_MEM>, 532 OpSize, Requires<[In64BitMode]>; 533 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", 534 [(store (add (loadi32 addr:$dst), -1), addr:$dst), 535 (implicit EFLAGS)], IIC_UNARY_MEM>, 536 Requires<[In64BitMode]>; 537 } // CodeSize = 2, SchedRW 538 539 let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { 540 let CodeSize = 2 in 541 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 542 "dec{b}\t$dst", 543 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))], 544 IIC_UNARY_REG>; 545 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. 546 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), 547 "dec{w}\t$dst", 548 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))], 549 IIC_UNARY_REG>, 550 OpSize, Requires<[In32BitMode]>; 551 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), 552 "dec{l}\t$dst", 553 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))], 554 IIC_UNARY_REG>, 555 Requires<[In32BitMode]>; 556 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst", 557 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))], 558 IIC_UNARY_REG>; 559 } // CodeSize = 2 560 } // Constraints = "$src1 = $dst", SchedRW 561 562 563 let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in { 564 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", 565 [(store (add (loadi8 addr:$dst), -1), addr:$dst), 566 (implicit EFLAGS)], IIC_UNARY_MEM>; 567 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", 568 [(store (add (loadi16 addr:$dst), -1), addr:$dst), 569 (implicit EFLAGS)], IIC_UNARY_MEM>, 570 OpSize, Requires<[In32BitMode]>; 571 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", 572 [(store (add (loadi32 addr:$dst), -1), addr:$dst), 573 (implicit EFLAGS)], IIC_UNARY_MEM>, 574 Requires<[In32BitMode]>; 575 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", 576 [(store (add (loadi64 addr:$dst), -1), addr:$dst), 577 (implicit EFLAGS)], IIC_UNARY_MEM>; 578 } // CodeSize = 2, SchedRW 579 } // Defs = [EFLAGS] 580 581 582 /// X86TypeInfo - This is a bunch of information that describes relevant X86 583 /// information about value types. For example, it can tell you what the 584 /// register class and preferred load to use. 585 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass, 586 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind, 587 Operand immoperand, SDPatternOperator immoperator, 588 Operand imm8operand, SDPatternOperator imm8operator, 589 bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> { 590 /// VT - This is the value type itself. 591 ValueType VT = vt; 592 593 /// InstrSuffix - This is the suffix used on instructions with this type. For 594 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q". 595 string InstrSuffix = instrsuffix; 596 597 /// RegClass - This is the register class associated with this type. For 598 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64. 599 RegisterClass RegClass = regclass; 600 601 /// LoadNode - This is the load node associated with this type. For 602 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64. 603 PatFrag LoadNode = loadnode; 604 605 /// MemOperand - This is the memory operand associated with this type. For 606 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem. 607 X86MemOperand MemOperand = memoperand; 608 609 /// ImmEncoding - This is the encoding of an immediate of this type. For 610 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32 611 /// since the immediate fields of i64 instructions is a 32-bit sign extended 612 /// value. 613 ImmType ImmEncoding = immkind; 614 615 /// ImmOperand - This is the operand kind of an immediate of this type. For 616 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 -> 617 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign 618 /// extended value. 619 Operand ImmOperand = immoperand; 620 621 /// ImmOperator - This is the operator that should be used to match an 622 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32). 623 SDPatternOperator ImmOperator = immoperator; 624 625 /// Imm8Operand - This is the operand kind to use for an imm8 of this type. 626 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is 627 /// only used for instructions that have a sign-extended imm8 field form. 628 Operand Imm8Operand = imm8operand; 629 630 /// Imm8Operator - This is the operator that should be used to match an 8-bit 631 /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8). 632 SDPatternOperator Imm8Operator = imm8operator; 633 634 /// HasOddOpcode - This bit is true if the instruction should have an odd (as 635 /// opposed to even) opcode. Operations on i8 are usually even, operations on 636 /// other datatypes are odd. 637 bit HasOddOpcode = hasOddOpcode; 638 639 /// HasOpSizePrefix - This bit is set to true if the instruction should have 640 /// the 0x66 operand size prefix. This is set for i16 types. 641 bit HasOpSizePrefix = hasOpSizePrefix; 642 643 /// HasREX_WPrefix - This bit is set to true if the instruction should have 644 /// the 0x40 REX prefix. This is set for i64 types. 645 bit HasREX_WPrefix = hasREX_WPrefix; 646 } 647 648 def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">; 649 650 651 def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem , 652 Imm8 , i8imm , imm, i8imm , invalid_node, 653 0, 0, 0>; 654 def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem, 655 Imm16, i16imm, imm, i16i8imm, i16immSExt8, 656 1, 1, 0>; 657 def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, 658 Imm32, i32imm, imm, i32i8imm, i32immSExt8, 659 1, 0, 0>; 660 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, 661 Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8, 662 1, 0, 1>; 663 664 /// ITy - This instruction base class takes the type info for the instruction. 665 /// Using this, it: 666 /// 1. Concatenates together the instruction mnemonic with the appropriate 667 /// suffix letter, a tab, and the arguments. 668 /// 2. Infers whether the instruction should have a 0x66 prefix byte. 669 /// 3. Infers whether the instruction should have a 0x40 REX_W prefix. 670 /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations) 671 /// or 1 (for i16,i32,i64 operations). 672 class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins, 673 string mnemonic, string args, list<dag> pattern, 674 InstrItinClass itin = IIC_BIN_NONMEM> 675 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4}, 676 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode }, 677 f, outs, ins, 678 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern, 679 itin> { 680 681 // Infer instruction prefixes from type info. 682 let hasOpSizePrefix = typeinfo.HasOpSizePrefix; 683 let hasREX_WPrefix = typeinfo.HasREX_WPrefix; 684 } 685 686 // BinOpRR - Instructions like "add reg, reg, reg". 687 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 688 dag outlist, list<dag> pattern, InstrItinClass itin, 689 Format f = MRMDestReg> 690 : ITy<opcode, f, typeinfo, outlist, 691 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2), 692 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>, 693 Sched<[WriteALU]>; 694 695 // BinOpRR_R - Instructions like "add reg, reg, reg", where the pattern has 696 // just a regclass (no eflags) as a result. 697 class BinOpRR_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 698 SDNode opnode> 699 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), 700 [(set typeinfo.RegClass:$dst, 701 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))], 702 IIC_BIN_NONMEM>; 703 704 // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has 705 // just a EFLAGS as a result. 706 class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 707 SDPatternOperator opnode, Format f = MRMDestReg> 708 : BinOpRR<opcode, mnemonic, typeinfo, (outs), 709 [(set EFLAGS, 710 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))], 711 IIC_BIN_NONMEM, f>; 712 713 // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has 714 // both a regclass and EFLAGS as a result. 715 class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 716 SDNode opnode> 717 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), 718 [(set typeinfo.RegClass:$dst, EFLAGS, 719 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))], 720 IIC_BIN_NONMEM>; 721 722 // BinOpRR_RFF - Instructions like "adc reg, reg, reg", where the pattern has 723 // both a regclass and EFLAGS as a result, and has EFLAGS as input. 724 class BinOpRR_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 725 SDNode opnode> 726 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), 727 [(set typeinfo.RegClass:$dst, EFLAGS, 728 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2, 729 EFLAGS))], IIC_BIN_NONMEM>; 730 731 // BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding). 732 class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo> 733 : ITy<opcode, MRMSrcReg, typeinfo, 734 (outs typeinfo.RegClass:$dst), 735 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2), 736 mnemonic, "{$src2, $dst|$dst, $src2}", [], IIC_BIN_NONMEM>, 737 Sched<[WriteALU]> { 738 // The disassembler should know about this, but not the asmparser. 739 let isCodeGenOnly = 1; 740 let hasSideEffects = 0; 741 } 742 743 // BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding). 744 class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo> 745 : ITy<opcode, MRMSrcReg, typeinfo, (outs), 746 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2), 747 mnemonic, "{$src2, $src1|$src1, $src2}", [], IIC_BIN_NONMEM>, 748 Sched<[WriteALU]> { 749 // The disassembler should know about this, but not the asmparser. 750 let isCodeGenOnly = 1; 751 let hasSideEffects = 0; 752 } 753 754 // BinOpRM - Instructions like "add reg, reg, [mem]". 755 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 756 dag outlist, list<dag> pattern> 757 : ITy<opcode, MRMSrcMem, typeinfo, outlist, 758 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2), 759 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_NONMEM>, 760 Sched<[WriteALULd, ReadAfterLd]>; 761 762 // BinOpRM_R - Instructions like "add reg, reg, [mem]". 763 class BinOpRM_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 764 SDNode opnode> 765 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), 766 [(set typeinfo.RegClass:$dst, 767 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>; 768 769 // BinOpRM_F - Instructions like "cmp reg, [mem]". 770 class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 771 SDPatternOperator opnode> 772 : BinOpRM<opcode, mnemonic, typeinfo, (outs), 773 [(set EFLAGS, 774 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>; 775 776 // BinOpRM_RF - Instructions like "add reg, reg, [mem]". 777 class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 778 SDNode opnode> 779 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), 780 [(set typeinfo.RegClass:$dst, EFLAGS, 781 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>; 782 783 // BinOpRM_RFF - Instructions like "adc reg, reg, [mem]". 784 class BinOpRM_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 785 SDNode opnode> 786 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), 787 [(set typeinfo.RegClass:$dst, EFLAGS, 788 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2), 789 EFLAGS))]>; 790 791 // BinOpRI - Instructions like "add reg, reg, imm". 792 class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 793 Format f, dag outlist, list<dag> pattern> 794 : ITy<opcode, f, typeinfo, outlist, 795 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2), 796 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_NONMEM>, 797 Sched<[WriteALU]> { 798 let ImmT = typeinfo.ImmEncoding; 799 } 800 801 // BinOpRI_R - Instructions like "add reg, reg, imm". 802 class BinOpRI_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 803 SDNode opnode, Format f> 804 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), 805 [(set typeinfo.RegClass:$dst, 806 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>; 807 808 // BinOpRI_F - Instructions like "cmp reg, imm". 809 class BinOpRI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 810 SDPatternOperator opnode, Format f> 811 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs), 812 [(set EFLAGS, 813 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>; 814 815 // BinOpRI_RF - Instructions like "add reg, reg, imm". 816 class BinOpRI_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 817 SDNode opnode, Format f> 818 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), 819 [(set typeinfo.RegClass:$dst, EFLAGS, 820 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>; 821 // BinOpRI_RFF - Instructions like "adc reg, reg, imm". 822 class BinOpRI_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 823 SDNode opnode, Format f> 824 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), 825 [(set typeinfo.RegClass:$dst, EFLAGS, 826 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2, 827 EFLAGS))]>; 828 829 // BinOpRI8 - Instructions like "add reg, reg, imm8". 830 class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 831 Format f, dag outlist, list<dag> pattern> 832 : ITy<opcode, f, typeinfo, outlist, 833 (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2), 834 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_NONMEM>, 835 Sched<[WriteALU]> { 836 let ImmT = Imm8; // Always 8-bit immediate. 837 } 838 839 // BinOpRI8_R - Instructions like "add reg, reg, imm8". 840 class BinOpRI8_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 841 SDNode opnode, Format f> 842 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), 843 [(set typeinfo.RegClass:$dst, 844 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>; 845 846 // BinOpRI8_F - Instructions like "cmp reg, imm8". 847 class BinOpRI8_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 848 SDNode opnode, Format f> 849 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs), 850 [(set EFLAGS, 851 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>; 852 853 // BinOpRI8_RF - Instructions like "add reg, reg, imm8". 854 class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 855 SDNode opnode, Format f> 856 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), 857 [(set typeinfo.RegClass:$dst, EFLAGS, 858 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>; 859 860 // BinOpRI8_RFF - Instructions like "adc reg, reg, imm8". 861 class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 862 SDNode opnode, Format f> 863 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), 864 [(set typeinfo.RegClass:$dst, EFLAGS, 865 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2, 866 EFLAGS))]>; 867 868 // BinOpMR - Instructions like "add [mem], reg". 869 class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 870 list<dag> pattern> 871 : ITy<opcode, MRMDestMem, typeinfo, 872 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src), 873 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM>, 874 Sched<[WriteALULd, WriteRMW]>; 875 876 // BinOpMR_RMW - Instructions like "add [mem], reg". 877 class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 878 SDNode opnode> 879 : BinOpMR<opcode, mnemonic, typeinfo, 880 [(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst), 881 (implicit EFLAGS)]>; 882 883 // BinOpMR_RMW_FF - Instructions like "adc [mem], reg". 884 class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 885 SDNode opnode> 886 : BinOpMR<opcode, mnemonic, typeinfo, 887 [(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS), 888 addr:$dst), 889 (implicit EFLAGS)]>; 890 891 // BinOpMR_F - Instructions like "cmp [mem], reg". 892 class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 893 SDNode opnode> 894 : BinOpMR<opcode, mnemonic, typeinfo, 895 [(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>; 896 897 // BinOpMI - Instructions like "add [mem], imm". 898 class BinOpMI<string mnemonic, X86TypeInfo typeinfo, 899 Format f, list<dag> pattern, bits<8> opcode = 0x80> 900 : ITy<opcode, f, typeinfo, 901 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src), 902 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM>, 903 Sched<[WriteALULd, WriteRMW]> { 904 let ImmT = typeinfo.ImmEncoding; 905 } 906 907 // BinOpMI_RMW - Instructions like "add [mem], imm". 908 class BinOpMI_RMW<string mnemonic, X86TypeInfo typeinfo, 909 SDNode opnode, Format f> 910 : BinOpMI<mnemonic, typeinfo, f, 911 [(store (opnode (typeinfo.VT (load addr:$dst)), 912 typeinfo.ImmOperator:$src), addr:$dst), 913 (implicit EFLAGS)]>; 914 // BinOpMI_RMW_FF - Instructions like "adc [mem], imm". 915 class BinOpMI_RMW_FF<string mnemonic, X86TypeInfo typeinfo, 916 SDNode opnode, Format f> 917 : BinOpMI<mnemonic, typeinfo, f, 918 [(store (opnode (typeinfo.VT (load addr:$dst)), 919 typeinfo.ImmOperator:$src, EFLAGS), addr:$dst), 920 (implicit EFLAGS)]>; 921 922 // BinOpMI_F - Instructions like "cmp [mem], imm". 923 class BinOpMI_F<string mnemonic, X86TypeInfo typeinfo, 924 SDPatternOperator opnode, Format f, bits<8> opcode = 0x80> 925 : BinOpMI<mnemonic, typeinfo, f, 926 [(set EFLAGS, (opnode (typeinfo.VT (load addr:$dst)), 927 typeinfo.ImmOperator:$src))], 928 opcode>; 929 930 // BinOpMI8 - Instructions like "add [mem], imm8". 931 class BinOpMI8<string mnemonic, X86TypeInfo typeinfo, 932 Format f, list<dag> pattern> 933 : ITy<0x82, f, typeinfo, 934 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src), 935 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM>, 936 Sched<[WriteALULd, WriteRMW]> { 937 let ImmT = Imm8; // Always 8-bit immediate. 938 } 939 940 // BinOpMI8_RMW - Instructions like "add [mem], imm8". 941 class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo, 942 SDNode opnode, Format f> 943 : BinOpMI8<mnemonic, typeinfo, f, 944 [(store (opnode (load addr:$dst), 945 typeinfo.Imm8Operator:$src), addr:$dst), 946 (implicit EFLAGS)]>; 947 948 // BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8". 949 class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo, 950 SDNode opnode, Format f> 951 : BinOpMI8<mnemonic, typeinfo, f, 952 [(store (opnode (load addr:$dst), 953 typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst), 954 (implicit EFLAGS)]>; 955 956 // BinOpMI8_F - Instructions like "cmp [mem], imm8". 957 class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo, 958 SDNode opnode, Format f> 959 : BinOpMI8<mnemonic, typeinfo, f, 960 [(set EFLAGS, (opnode (load addr:$dst), 961 typeinfo.Imm8Operator:$src))]>; 962 963 // BinOpAI - Instructions like "add %eax, %eax, imm", that imp-def EFLAGS. 964 class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 965 Register areg, string operands> 966 : ITy<opcode, RawFrm, typeinfo, 967 (outs), (ins typeinfo.ImmOperand:$src), 968 mnemonic, operands, []>, Sched<[WriteALU]> { 969 let ImmT = typeinfo.ImmEncoding; 970 let Uses = [areg]; 971 let Defs = [areg, EFLAGS]; 972 let hasSideEffects = 0; 973 } 974 975 // BinOpAI_FF - Instructions like "adc %eax, %eax, imm", that implicitly define 976 // and use EFLAGS. 977 class BinOpAI_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, 978 Register areg, string operands> 979 : BinOpAI<opcode, mnemonic, typeinfo, areg, operands> { 980 let Uses = [areg, EFLAGS]; 981 } 982 983 /// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is 984 /// defined with "(set GPR:$dst, EFLAGS, (...". 985 /// 986 /// It would be nice to get rid of the second and third argument here, but 987 /// tblgen can't handle dependent type references aggressively enough: PR8330 988 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, 989 string mnemonic, Format RegMRM, Format MemMRM, 990 SDNode opnodeflag, SDNode opnode, 991 bit CommutableRR, bit ConvertibleToThreeAddress> { 992 let Defs = [EFLAGS] in { 993 let Constraints = "$src1 = $dst" in { 994 let isCommutable = CommutableRR, 995 isConvertibleToThreeAddress = ConvertibleToThreeAddress in { 996 def NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>; 997 def NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>; 998 def NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>; 999 def NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>; 1000 } // isCommutable 1001 1002 def NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>; 1003 def NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>; 1004 def NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>; 1005 def NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>; 1006 1007 def NAME#8rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi8 , opnodeflag>; 1008 def NAME#16rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, opnodeflag>; 1009 def NAME#32rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>; 1010 def NAME#64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>; 1011 1012 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { 1013 // NOTE: These are order specific, we want the ri8 forms to be listed 1014 // first so that they are slightly preferred to the ri forms. 1015 def NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>; 1016 def NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>; 1017 def NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>; 1018 1019 def NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>; 1020 def NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>; 1021 def NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>; 1022 def NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>; 1023 } 1024 } // Constraints = "$src1 = $dst" 1025 1026 def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>; 1027 def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>; 1028 def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>; 1029 def NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>; 1030 1031 // NOTE: These are order specific, we want the mi8 forms to be listed 1032 // first so that they are slightly preferred to the mi forms. 1033 def NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>; 1034 def NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>; 1035 def NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>; 1036 1037 def NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>; 1038 def NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>; 1039 def NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>; 1040 def NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>; 1041 } // Defs = [EFLAGS] 1042 1043 def NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL, 1044 "{$src, %al|al, $src}">; 1045 def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX, 1046 "{$src, %ax|ax, $src}">; 1047 def NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX, 1048 "{$src, %eax|eax, $src}">; 1049 def NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX, 1050 "{$src, %rax|rax, $src}">; 1051 } 1052 1053 /// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is 1054 /// defined with "(set GPR:$dst, EFLAGS, (node LHS, RHS, EFLAGS))" like ADC and 1055 /// SBB. 1056 /// 1057 /// It would be nice to get rid of the second and third argument here, but 1058 /// tblgen can't handle dependent type references aggressively enough: PR8330 1059 multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, 1060 string mnemonic, Format RegMRM, Format MemMRM, 1061 SDNode opnode, bit CommutableRR, 1062 bit ConvertibleToThreeAddress> { 1063 let Uses = [EFLAGS], Defs = [EFLAGS] in { 1064 let Constraints = "$src1 = $dst" in { 1065 let isCommutable = CommutableRR, 1066 isConvertibleToThreeAddress = ConvertibleToThreeAddress in { 1067 def NAME#8rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi8 , opnode>; 1068 def NAME#16rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi16, opnode>; 1069 def NAME#32rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi32, opnode>; 1070 def NAME#64rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi64, opnode>; 1071 } // isCommutable 1072 1073 def NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>; 1074 def NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>; 1075 def NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>; 1076 def NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>; 1077 1078 def NAME#8rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi8 , opnode>; 1079 def NAME#16rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi16, opnode>; 1080 def NAME#32rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi32, opnode>; 1081 def NAME#64rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi64, opnode>; 1082 1083 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { 1084 // NOTE: These are order specific, we want the ri8 forms to be listed 1085 // first so that they are slightly preferred to the ri forms. 1086 def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>; 1087 def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>; 1088 def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>; 1089 1090 def NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>; 1091 def NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>; 1092 def NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>; 1093 def NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>; 1094 } 1095 } // Constraints = "$src1 = $dst" 1096 1097 def NAME#8mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi8 , opnode>; 1098 def NAME#16mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi16, opnode>; 1099 def NAME#32mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi32, opnode>; 1100 def NAME#64mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi64, opnode>; 1101 1102 // NOTE: These are order specific, we want the mi8 forms to be listed 1103 // first so that they are slightly preferred to the mi forms. 1104 def NAME#16mi8 : BinOpMI8_RMW_FF<mnemonic, Xi16, opnode, MemMRM>; 1105 def NAME#32mi8 : BinOpMI8_RMW_FF<mnemonic, Xi32, opnode, MemMRM>; 1106 def NAME#64mi8 : BinOpMI8_RMW_FF<mnemonic, Xi64, opnode, MemMRM>; 1107 1108 def NAME#8mi : BinOpMI_RMW_FF<mnemonic, Xi8 , opnode, MemMRM>; 1109 def NAME#16mi : BinOpMI_RMW_FF<mnemonic, Xi16, opnode, MemMRM>; 1110 def NAME#32mi : BinOpMI_RMW_FF<mnemonic, Xi32, opnode, MemMRM>; 1111 def NAME#64mi32 : BinOpMI_RMW_FF<mnemonic, Xi64, opnode, MemMRM>; 1112 } // Uses = [EFLAGS], Defs = [EFLAGS] 1113 1114 def NAME#8i8 : BinOpAI_FF<BaseOpc4, mnemonic, Xi8 , AL, 1115 "{$src, %al|al, $src}">; 1116 def NAME#16i16 : BinOpAI_FF<BaseOpc4, mnemonic, Xi16, AX, 1117 "{$src, %ax|ax, $src}">; 1118 def NAME#32i32 : BinOpAI_FF<BaseOpc4, mnemonic, Xi32, EAX, 1119 "{$src, %eax|eax, $src}">; 1120 def NAME#64i32 : BinOpAI_FF<BaseOpc4, mnemonic, Xi64, RAX, 1121 "{$src, %rax|rax, $src}">; 1122 } 1123 1124 /// ArithBinOp_F - This is an arithmetic binary operator where the pattern is 1125 /// defined with "(set EFLAGS, (...". It would be really nice to find a way 1126 /// to factor this with the other ArithBinOp_*. 1127 /// 1128 multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, 1129 string mnemonic, Format RegMRM, Format MemMRM, 1130 SDNode opnode, 1131 bit CommutableRR, bit ConvertibleToThreeAddress> { 1132 let Defs = [EFLAGS] in { 1133 let isCommutable = CommutableRR, 1134 isConvertibleToThreeAddress = ConvertibleToThreeAddress in { 1135 def NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>; 1136 def NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>; 1137 def NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>; 1138 def NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>; 1139 } // isCommutable 1140 1141 def NAME#8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>; 1142 def NAME#16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>; 1143 def NAME#32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>; 1144 def NAME#64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>; 1145 1146 def NAME#8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>; 1147 def NAME#16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>; 1148 def NAME#32rm : BinOpRM_F<BaseOpc2, mnemonic, Xi32, opnode>; 1149 def NAME#64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>; 1150 1151 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { 1152 // NOTE: These are order specific, we want the ri8 forms to be listed 1153 // first so that they are slightly preferred to the ri forms. 1154 def NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>; 1155 def NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>; 1156 def NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>; 1157 1158 def NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>; 1159 def NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>; 1160 def NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>; 1161 def NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>; 1162 } 1163 1164 def NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>; 1165 def NAME#16mr : BinOpMR_F<BaseOpc, mnemonic, Xi16, opnode>; 1166 def NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>; 1167 def NAME#64mr : BinOpMR_F<BaseOpc, mnemonic, Xi64, opnode>; 1168 1169 // NOTE: These are order specific, we want the mi8 forms to be listed 1170 // first so that they are slightly preferred to the mi forms. 1171 def NAME#16mi8 : BinOpMI8_F<mnemonic, Xi16, opnode, MemMRM>; 1172 def NAME#32mi8 : BinOpMI8_F<mnemonic, Xi32, opnode, MemMRM>; 1173 def NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, opnode, MemMRM>; 1174 1175 def NAME#8mi : BinOpMI_F<mnemonic, Xi8 , opnode, MemMRM>; 1176 def NAME#16mi : BinOpMI_F<mnemonic, Xi16, opnode, MemMRM>; 1177 def NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>; 1178 def NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>; 1179 } // Defs = [EFLAGS] 1180 1181 def NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL, 1182 "{$src, %al|al, $src}">; 1183 def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX, 1184 "{$src, %ax|ax, $src}">; 1185 def NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX, 1186 "{$src, %eax|eax, $src}">; 1187 def NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX, 1188 "{$src, %rax|rax, $src}">; 1189 } 1190 1191 1192 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m, 1193 X86and_flag, and, 1, 0>; 1194 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m, 1195 X86or_flag, or, 1, 0>; 1196 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m, 1197 X86xor_flag, xor, 1, 0>; 1198 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m, 1199 X86add_flag, add, 1, 1>; 1200 let isCompare = 1 in { 1201 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m, 1202 X86sub_flag, sub, 0, 0>; 1203 } 1204 1205 // Arithmetic. 1206 defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag, 1207 1, 0>; 1208 defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag, 1209 0, 0>; 1210 1211 let isCompare = 1 in { 1212 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>; 1213 } 1214 1215 1216 //===----------------------------------------------------------------------===// 1217 // Semantically, test instructions are similar like AND, except they don't 1218 // generate a result. From an encoding perspective, they are very different: 1219 // they don't have all the usual imm8 and REV forms, and are encoded into a 1220 // different space. 1221 def X86testpat : PatFrag<(ops node:$lhs, node:$rhs), 1222 (X86cmp (and_su node:$lhs, node:$rhs), 0)>; 1223 1224 let isCompare = 1 in { 1225 let Defs = [EFLAGS] in { 1226 let isCommutable = 1 in { 1227 def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>; 1228 def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>; 1229 def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>; 1230 def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>; 1231 } // isCommutable 1232 1233 def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>; 1234 def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>; 1235 def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>; 1236 def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>; 1237 1238 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>; 1239 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>; 1240 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>; 1241 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>; 1242 1243 def TEST8mi : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>; 1244 def TEST16mi : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>; 1245 def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>; 1246 def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>; 1247 1248 // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the 1249 // register class is constrained to GR8_NOREX. 1250 let isPseudo = 1 in 1251 def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask), 1252 "", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>; 1253 } // Defs = [EFLAGS] 1254 1255 def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL, 1256 "{$src, %al|al, $src}">; 1257 def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX, 1258 "{$src, %ax|ax, $src}">; 1259 def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX, 1260 "{$src, %eax|eax, $src}">; 1261 def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX, 1262 "{$src, %rax|rax, $src}">; 1263 } // isCompare 1264 1265 //===----------------------------------------------------------------------===// 1266 // ANDN Instruction 1267 // 1268 multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop, 1269 PatFrag ld_frag> { 1270 def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 1271 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1272 [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))], 1273 IIC_BIN_NONMEM>, Sched<[WriteALU]>; 1274 def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 1275 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1276 [(set RC:$dst, EFLAGS, 1277 (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))], IIC_BIN_MEM>, 1278 Sched<[WriteALULd, ReadAfterLd]>; 1279 } 1280 1281 let Predicates = [HasBMI], Defs = [EFLAGS] in { 1282 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V; 1283 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W; 1284 } 1285 1286 let Predicates = [HasBMI] in { 1287 def : Pat<(and (not GR32:$src1), GR32:$src2), 1288 (ANDN32rr GR32:$src1, GR32:$src2)>; 1289 def : Pat<(and (not GR64:$src1), GR64:$src2), 1290 (ANDN64rr GR64:$src1, GR64:$src2)>; 1291 def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)), 1292 (ANDN32rm GR32:$src1, addr:$src2)>; 1293 def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)), 1294 (ANDN64rm GR64:$src1, addr:$src2)>; 1295 } 1296 1297 //===----------------------------------------------------------------------===// 1298 // MULX Instruction 1299 // 1300 multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop> { 1301 let neverHasSideEffects = 1 in { 1302 let isCommutable = 1 in 1303 def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src), 1304 !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), 1305 [], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMul, WriteIMulH]>; 1306 1307 let mayLoad = 1 in 1308 def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src), 1309 !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), 1310 [], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMulLd, WriteIMulH]>; 1311 } 1312 } 1313 1314 let Predicates = [HasBMI2] in { 1315 let Uses = [EDX] in 1316 defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem>; 1317 let Uses = [RDX] in 1318 defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem>, VEX_W; 1319 } 1320 1321 //===----------------------------------------------------------------------===// 1322 // ADCX Instruction 1323 // 1324 let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in { 1325 let SchedRW = [WriteALU] in { 1326 def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1327 "adcx{l}\t{$src, $dst|$dst, $src}", 1328 [], IIC_BIN_NONMEM>, T8, OpSize; 1329 1330 def ADCX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1331 "adcx{q}\t{$src, $dst|$dst, $src}", 1332 [], IIC_BIN_NONMEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>; 1333 } // SchedRW 1334 1335 let mayLoad = 1, SchedRW = [WriteALULd] in { 1336 def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1337 "adcx{l}\t{$src, $dst|$dst, $src}", 1338 [], IIC_BIN_MEM>, T8, OpSize; 1339 1340 def ADCX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1341 "adcx{q}\t{$src, $dst|$dst, $src}", 1342 [], IIC_BIN_MEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>; 1343 } 1344 } 1345 1346 //===----------------------------------------------------------------------===// 1347 // ADOX Instruction 1348 // 1349 let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in { 1350 let SchedRW = [WriteALU] in { 1351 def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1352 "adox{l}\t{$src, $dst|$dst, $src}", 1353 [], IIC_BIN_NONMEM>, T8XS; 1354 1355 def ADOX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1356 "adox{q}\t{$src, $dst|$dst, $src}", 1357 [], IIC_BIN_NONMEM>, T8XS, REX_W, Requires<[In64BitMode]>; 1358 } // SchedRW 1359 1360 let mayLoad = 1, SchedRW = [WriteALULd] in { 1361 def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1362 "adox{l}\t{$src, $dst|$dst, $src}", 1363 [], IIC_BIN_MEM>, T8XS; 1364 1365 def ADOX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1366 "adox{q}\t{$src, $dst|$dst, $src}", 1367 [], IIC_BIN_MEM>, T8XS, REX_W, Requires<[In64BitMode]>; 1368 } 1369 } 1370
