1 # RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s 2 3 # This file is checking Thumbv7 encodings which are globally invalid, usually due 4 # to the constraints of the instructions not being met. For example invalid 5 # combinations of registers. 6 7 #------------------------------------------------------------------------------ 8 # Undefined encoding for b.cc 9 #------------------------------------------------------------------------------ 10 11 # Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) 12 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13 # ------------------------------------------------------------------------------------------------- 14 # | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| 15 # ------------------------------------------------------------------------------------------------- 16 # 17 # A8.6.16 B 18 # if cond<3:1> == '111' then SEE "Related Encodings" 19 20 [0xaf 0xf7 0x44 0x8b] 21 # CHECK: warning: invalid instruction encoding 22 # CHECK-NEXT: [0xaf 0xf7 0x44 0x8b] 23 24 # Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) 25 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 26 # ------------------------------------------------------------------------------------------------- 27 # | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| 28 # ------------------------------------------------------------------------------------------------- 29 # 30 # if cond = '1110' then UNDEFINED 31 [0x6f 0xde] 32 # CHECK: invalid instruction encoding 33 # CHECK-NEXT: [0x6f 0xde] 34 35 36 #------------------------------------------------------------------------------ 37 # Undefined encoding space for hint instructions 38 #------------------------------------------------------------------------------ 39 40 [0xaf 0xf3 0x05 0x80] 41 # CHECK: invalid instruction encoding 42 # CHECK-NEXT: [0xaf 0xf3 0x05 0x80] 43 44 45 #------------------------------------------------------------------------------ 46 # Undefined encoding for it 47 #------------------------------------------------------------------------------ 48 49 [0xff 0xbf 0x6b 0x80 0x00 0x75] 50 # CHECK: potentially undefined instruction encoding 51 # CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75] 52 53 # mask = 0 54 [0x50 0xbf 0x00 0x00] 55 # CHECK: invalid instruction encoding 56 # CHECK-NEXT: [0x50 0xbf 0x00 0x00] 57 58 # Two warnings from this block since there are two instructions in there 59 [0xdb 0xbf 0x42 0xbb] 60 # CHECK: potentially undefined instruction encoding 61 # CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] 62 # CHECK: potentially undefined instruction encoding 63 # CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] 64 65 #------------------------------------------------------------------------------ 66 # Undefined encoding for ldm 67 #------------------------------------------------------------------------------ 68 69 # Writeback is not allowed is Rn is in the target register list. 70 [0xb4 0xe8 0x34 0x04] 71 # CHECK: potentially undefined instruction encoding 72 # CHECK-NEXT: [0xb4 0xe8 0x34 0x04] 73 74 75 #------------------------------------------------------------------------------ 76 # Undefined encoding for ldrd 77 #------------------------------------------------------------------------------ 78 79 # Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) 80 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 81 # ------------------------------------------------------------------------------------------------- 82 # | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 83 # ------------------------------------------------------------------------------------------------- 84 # 85 # A8.6.66 LDRD (immediate) 86 # if Rn = '1111' then SEE LDRD (literal) 87 # A8.6.67 LDRD (literal) 88 # Inst{21} = 0 89 90 [0xff 0xe9 0x0 0xeb] 91 # CHECK: potentially undefined 92 # CHECK-NEXT: [0xff 0xe9 0x0 0xeb] 93 94 95 #------------------------------------------------------------------------------ 96 # Undefined encodings for ldrbt 97 #------------------------------------------------------------------------------ 98 99 # Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) 100 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 101 # ------------------------------------------------------------------------------------------------- 102 # | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 103 # ------------------------------------------------------------------------------------------------- 104 # 105 # The unpriviledged Load/Store cannot have SP or PC as Rt. 106 [0x10 0xf8 0x3 0xfe] 107 # CHECK: potentially undefined instruction encoding 108 # CHECK-NEXT: [0x10 0xf8 0x3 0xfe] 109 110 111 #------------------------------------------------------------------------------ 112 # Undefined encodings for ldrsh 113 #------------------------------------------------------------------------------ 114 115 # invalid LDRSHs Rt=PC 116 [0x30 0xf9 0x00 0xf0] 117 # CHECK: invalid instruction encoding 118 # CHECK-NEXT: [0x30 0xf9 0x00 0xf0] 119 120 # invalid LDRSHi8 Rt=PC 121 [0x30 0xf9 0x00 0xfc] 122 # CHECK: invalid instruction encoding 123 # CHECK-NEXT: [0x30 0xf9 0x00 0xfc] 124 125 # invalid LDRSHi12 Rt=PC 126 [0xb0 0xf9 0x00 0xf0] 127 # CHECK: invalid instruction encoding 128 # CHECK-NEXT: [0xb0 0xf9 0x00 0xf0] 129 130 # Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) 131 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 132 # ------------------------------------------------------------------------------------------------- 133 # | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 134 # ------------------------------------------------------------------------------------------------- 135 # 136 # if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" 137 [0x35 0xf9 0x00 0xfc] 138 # CHECK: invalid instruction encoding 139 # CHECK-NEXT: [0x35 0xf9 0x00 0xfc] 140 141 # Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) 142 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 143 # ------------------------------------------------------------------------------------------------- 144 # | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| 145 # ------------------------------------------------------------------------------------------------- 146 # 147 # if Rt = '1111' then SEE "Unallocated memory hints" 148 [0xb3 0xf9 0xdf 0xf8] 149 # CHECK: invalid instruction encoding 150 # CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8] 151 152 153 #------------------------------------------------------------------------------ 154 # Undefined encoding for push 155 #------------------------------------------------------------------------------ 156 157 # SP and PC are not allowed in the register list on STM instructions in Thumb2. 158 [0x2d 0xe9 0xf7 0xb6] 159 # CHECK: invalid instruction encoding 160 # CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6] 161 162 163 #------------------------------------------------------------------------------ 164 # Undefined encoding for stmia 165 #------------------------------------------------------------------------------ 166 167 # Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) 168 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 169 # ------------------------------------------------------------------------------------------------- 170 # | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 171 # ------------------------------------------------------------------------------------------------- 172 # 173 # if BitCount(registers) < 1 then UNPREDICTABLE 174 [0x00 0xc7] 175 # CHECK: invalid instruction encoding 176 # CHECK-NEXT: [0x00 0xc7] 177 178 179 #------------------------------------------------------------------------------ 180 # Undefined encodings for str 181 #------------------------------------------------------------------------------ 182 183 # invalid STRi12 Rn=PC 184 [0xcf 0xf8 0x00 0x00] 185 # CHECK: invalid instruction encoding 186 # CHECK-NEXT: [0xcf 0xf8 0x00 0x00] 187 188 # invalid STRi8 Rn=PC 189 [0x4f 0xf8 0x00 0x0c] 190 # CHECK: invalid instruction encoding 191 # CHECK-NEXT: [0x4f 0xf8 0x00 0x0c] 192 193 # invalid STRs Rn=PC 194 [0x4f 0xf8 0x00 0x00] 195 # CHECK: invalid instruction encoding 196 # CHECK-NEXT: [0x4f 0xf8 0x00 0x00] 197 198 # invalid STRBi12 Rn=PC 199 [0x0f 0xf8 0x00 0x00] 200 # CHECK: invalid instruction encoding 201 # CHECK-NEXT: [0x0f 0xf8 0x00 0x00] 202 203 # invalid STRBi8 Rn=PC 204 [0x0f 0xf8 0x00 0x0c] 205 # CHECK: invalid instruction encoding 206 # CHECK-NEXT: [0x0f 0xf8 0x00 0x0c] 207 208 # invalid STRBs Rn=PC 209 [0x0f 0xf8 0x00 0x00] 210 # CHECK: invalid instruction encoding 211 # CHECK-NEXT: [0x0f 0xf8 0x00 0x00] 212 213 # invalid STRHi12 Rn=PC 214 [0xaf 0xf8 0x00 0x00] 215 # CHECK: invalid instruction encoding 216 # CHECK-NEXT: [0xaf 0xf8 0x00 0x00] 217 218 # invalid STRHi8 Rn=PC 219 [0x2f 0xf8 0x00 0x0c] 220 # CHECK: invalid instruction encoding 221 # CHECK-NEXT: [0x2f 0xf8 0x00 0x0c] 222 223 # invalid STRHs Rn=PC 224 [0x2f 0xf8 0x00 0x00] 225 # CHECK: invalid instruction encoding 226 # CHECK-NEXT: [0x2f 0xf8 0x00 0x00] 227 228 # invalid STRBT Rn=PC 229 [0x0f 0xf8 0x00 0x0e] 230 # CHECK: invalid instruction encoding 231 # CHECK-NEXT: [0x0f 0xf8 0x00 0x0e] 232 233 # invalid STRHT Rn=PC 234 [0x2f 0xf8 0x00 0x0e] 235 # CHECK: invalid instruction encoding 236 # CHECK-NEXT: [0x2f 0xf8 0x00 0x0e] 237 238 # invalid STRT Rn=PC 239 [0x4f 0xf8 0x00 0x0e] 240 # CHECK: invalid instruction encoding 241 # CHECK-NEXT: [0x4f 0xf8 0x00 0x0e] 242 243 # Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) 244 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 245 # ------------------------------------------------------------------------------------------------- 246 # | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 247 # ------------------------------------------------------------------------------------------------- 248 # 249 # if Rn == '1111' then UNDEFINED 250 251 [0x4f 0xf8 0xff 0xeb] 252 # CHECK: invalid instruction encoding 253 # CHECK-NEXT: [0x4f 0xf8 0xff 0xeb] 254 255 #------------------------------------------------------------------------------ 256 # Undefined encodings for strd 257 #------------------------------------------------------------------------------ 258 259 # Rt == Rn is UNPREDICTABLE 260 [0xe4 0xe9 0x02 0x46] 261 # CHECK: warning: potentially undefined instruction encoding 262 # CHECK-NEXT: [0xe4 0xe9 0x02 0x46] 263 264 #------------------------------------------------------------------------------ 265 # Undefined encodings for NEON/VFP instructions with invalid predicate bits 266 #------------------------------------------------------------------------------ 267 268 # VABS 269 [0x40 0xde 0x00 0x0a] 270 # CHECK: invalid instruction encoding 271 # CHECK-NEXT: [0x40 0xde 0x00 0x0a] 272 273 274 # VMLA 275 [0xf0 0xde 0xe0 0x0b] 276 # CHECK: invalid instruction encoding 277 # CHECK-NEXT: [0xf0 0xde 0xe0 0x0b] 278 279 # VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) 280 281 # VMOV 282 [0x00 0xde 0x10 0x0b] 283 # CHECK: invalid instruction encoding 284 # CHECK-NEXT: [0x00 0xde 0x10 0x0b] 285 286 # VDUP 287 [0xff 0xde 0xf0 0xfb] 288 # CHECK: invalid instruction encoding 289 # CHECK-NEXT: [0xff 0xde 0xf0 0xfb] 290 291 292 #------------------------------------------------------------------------------ 293 # Undefined encodings for NEON vld instructions 294 #------------------------------------------------------------------------------ 295 296 # size = '00' and index_align == '0001' so UNDEFINED 297 [0xa0 0xf9 0x10 0x08] 298 # CHECK: invalid instruction encoding 299 # CHECK-NEXT: [0xa0 0xf9 0x10 0x08] 300 301 302 # vld3 303 304 # Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) 305 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 306 # ------------------------------------------------------------------------------------------------- 307 # | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| 308 # ------------------------------------------------------------------------------------------------- 309 # 310 # A8.6.315 VLD3 (single 3-element structure to all lanes) 311 # The a bit must be encoded as 0. 312 313 [0xa2 0xf9 0x92 0x2e] 314 # CHECK: invalid instruction encoding 315 # CHECK-NEXT: [0xa2 0xf9 0x92 0x2e] 316 317 318 # Some vld4 ones 319 # size == '11' and a == '0' so UNDEFINED 320 [0xa0 0xf9 0xc0 0x0f] 321 # CHECK: invalid instruction encoding 322 # CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f] 323 324 [0xa0 0xf9 0x30 0x0b] 325 # CHECK: invalid instruction encoding 326 # CHECK-NEXT: [0xa0 0xf9 0x30 0x0b] 327 328 329 # VLD1 multi-element, type=0b1010 align=0b11 330 [0x24 0xf9 0xbf 0x8a] 331 # CHECK: invalid instruction encoding 332 # CHECK-NEXT: [0x24 0xf9 0xbf 0x8a] 333 334 # VLD1 multi-element type=0b0111 align=0b1x 335 [0x24 0xf9 0xbf 0x87] 336 # CHECK: invalid instruction encoding 337 # CHECK-NEXT: [0x24 0xf9 0xbf 0x87] 338 339 # VLD1 multi-element type=0b0010 align=0b1x 340 [0x24 0xf9 0xbf 0x86] 341 # CHECK: invalid instruction encoding 342 # CHECK-NEXT: [0x24 0xf9 0xbf 0x86] 343 344 # VLD2 multi-element size=0b11 345 [0x60 0xf9 0xcf 0x08] 346 # CHECK: invalid instruction encoding 347 # CHECK-NEXT: [0x60 0xf9 0xcf 0x08] 348 349 # VLD2 multi-element type=0b1111 align=0b11 350 [0x60 0xf9 0xbf 0x08] 351 # CHECK: invalid instruction encoding 352 # CHECK-NEXT: [0x60 0xf9 0xbf 0x08] 353 354 # VLD2 multi-element type=0b1001 align=0b11 355 [0x60 0xf9 0xbf 0x09] 356 # CHECK: invalid instruction encoding 357 # CHECK-NEXT: [0x60 0xf9 0xbf 0x09] 358 359 # VLD3 multi-element size=0b11 360 [0x60 0xf9 0x7f 0x04] 361 # CHECK: invalid instruction encoding 362 # CHECK-NEXT: [0x60 0xf9 0x7f 0x04] 363 364 # VLD3 multi-element align=0b1x 365 [0x60 0xf9 0xcf 0x04] 366 # CHECK: invalid instruction encoding 367 # CHECK-NEXT: [0x60 0xf9 0xcf 0x04] 368 369 # VLD4 multi-element size=0b11 370 [0x60 0xf9 0xcd 0x11] 371 # CHECK: invalid instruction encoding 372 # CHECK-NEXT: [0x60 0xf9 0xcd 0x11] 373 374 375 #------------------------------------------------------------------------------ 376 # Undefined encodings for NEON vst1 377 #------------------------------------------------------------------------------ 378 379 # size == '10' and index_align == '0001' so UNDEFINED 380 [0x80 0xf9 0x10 0x08] 381 # CHECK: invalid instruction encoding 382 # CHECK-NEXT: [0x80 0xf9 0x10 0x08] 383 384 # Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) 385 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 386 # ------------------------------------------------------------------------------------------------- 387 # | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| 388 # ------------------------------------------------------------------------------------------------- 389 # 390 # A8.6.391 VST1 (multiple single elements) 391 # This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128] 392 # But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> 393 # contains two or four registers. rdar://11220250 394 [0x00 0xf9 0x2f 0x06] 395 # CHECK: invalid instruction encoding 396 # CHECK-NEXT: [0x00 0xf9 0x2f 0x06] 397 398 #------------------------------------------------------------------------------ 399 # Undefined encodings for NEON vst4 400 #------------------------------------------------------------------------------ 401 402 [0x80 0xf9 0x30 0x0b] 403 # CHECK: invalid instruction encoding 404 # CHECK-NEXT: [0x80 0xf9 0x30 0x0b] 405
