1 /* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude (at) gmail.com> 3 * Copyright 2009 Marek Olk <maraeo (at) gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24 /* r300_emit: Functions for emitting state. */ 25 26 #include "util/u_format.h" 27 #include "util/u_math.h" 28 #include "util/u_mm.h" 29 30 #include "r300_context.h" 31 #include "r300_cb.h" 32 #include "r300_cs.h" 33 #include "r300_emit.h" 34 #include "r300_fs.h" 35 #include "r300_screen.h" 36 #include "r300_screen_buffer.h" 37 #include "r300_vs.h" 38 39 void r300_emit_blend_state(struct r300_context* r300, 40 unsigned size, void* state) 41 { 42 struct r300_blend_state* blend = (struct r300_blend_state*)state; 43 struct pipe_framebuffer_state* fb = 44 (struct pipe_framebuffer_state*)r300->fb_state.state; 45 CS_LOCALS(r300); 46 47 if (fb->nr_cbufs) { 48 if (fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT) { 49 WRITE_CS_TABLE(blend->cb_noclamp, size); 50 } else { 51 unsigned swz = r300_surface(fb->cbufs[0])->colormask_swizzle; 52 WRITE_CS_TABLE(blend->cb_clamp[swz], size); 53 } 54 } else { 55 WRITE_CS_TABLE(blend->cb_no_readwrite, size); 56 } 57 } 58 59 void r300_emit_blend_color_state(struct r300_context* r300, 60 unsigned size, void* state) 61 { 62 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state; 63 CS_LOCALS(r300); 64 65 WRITE_CS_TABLE(bc->cb, size); 66 } 67 68 void r300_emit_clip_state(struct r300_context* r300, 69 unsigned size, void* state) 70 { 71 struct r300_clip_state* clip = (struct r300_clip_state*)state; 72 CS_LOCALS(r300); 73 74 WRITE_CS_TABLE(clip->cb, size); 75 } 76 77 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state) 78 { 79 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state; 80 struct pipe_framebuffer_state* fb = 81 (struct pipe_framebuffer_state*)r300->fb_state.state; 82 CS_LOCALS(r300); 83 84 if (fb->zsbuf) { 85 if (fb->nr_cbufs && fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT) 86 WRITE_CS_TABLE(&dsa->cb_begin_fp16, size); 87 else 88 WRITE_CS_TABLE(&dsa->cb_begin, size); 89 } else { 90 if (fb->nr_cbufs && fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT) 91 WRITE_CS_TABLE(dsa->cb_fp16_zb_no_readwrite, size); 92 else 93 WRITE_CS_TABLE(dsa->cb_zb_no_readwrite, size); 94 } 95 } 96 97 static void get_rc_constant_state( 98 float vec[4], 99 struct r300_context * r300, 100 struct rc_constant * constant) 101 { 102 struct r300_textures_state* texstate = r300->textures_state.state; 103 struct r300_resource *tex; 104 105 assert(constant->Type == RC_CONSTANT_STATE); 106 107 /* vec should either be (0, 0, 0, 1), which should be a relatively safe 108 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE 109 * state factors. */ 110 111 switch (constant->u.State[0]) { 112 /* Factor for converting rectangle coords to 113 * normalized coords. Should only show up on non-r500. */ 114 case RC_STATE_R300_TEXRECT_FACTOR: 115 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture); 116 vec[0] = 1.0 / tex->tex.width0; 117 vec[1] = 1.0 / tex->tex.height0; 118 vec[2] = 0; 119 vec[3] = 1; 120 break; 121 122 case RC_STATE_R300_TEXSCALE_FACTOR: 123 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture); 124 /* Add a small number to the texture size to work around rounding errors in hw. */ 125 vec[0] = tex->b.b.width0 / (tex->tex.width0 + 0.001f); 126 vec[1] = tex->b.b.height0 / (tex->tex.height0 + 0.001f); 127 vec[2] = tex->b.b.depth0 / (tex->tex.depth0 + 0.001f); 128 vec[3] = 1; 129 break; 130 131 case RC_STATE_R300_VIEWPORT_SCALE: 132 vec[0] = r300->viewport.scale[0]; 133 vec[1] = r300->viewport.scale[1]; 134 vec[2] = r300->viewport.scale[2]; 135 vec[3] = 1; 136 break; 137 138 case RC_STATE_R300_VIEWPORT_OFFSET: 139 vec[0] = r300->viewport.translate[0]; 140 vec[1] = r300->viewport.translate[1]; 141 vec[2] = r300->viewport.translate[2]; 142 vec[3] = 1; 143 break; 144 145 default: 146 fprintf(stderr, "r300: Implementation error: " 147 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]); 148 vec[0] = 0; 149 vec[1] = 0; 150 vec[2] = 0; 151 vec[3] = 1; 152 } 153 } 154 155 /* Convert a normal single-precision float into the 7.16 format 156 * used by the R300 fragment shader. 157 */ 158 uint32_t pack_float24(float f) 159 { 160 union { 161 float fl; 162 uint32_t u; 163 } u; 164 float mantissa; 165 int exponent; 166 uint32_t float24 = 0; 167 168 if (f == 0.0) 169 return 0; 170 171 u.fl = f; 172 173 mantissa = frexpf(f, &exponent); 174 175 /* Handle -ve */ 176 if (mantissa < 0) { 177 float24 |= (1 << 23); 178 mantissa = mantissa * -1.0; 179 } 180 /* Handle exponent, bias of 63 */ 181 exponent += 62; 182 float24 |= (exponent << 16); 183 /* Kill 7 LSB of mantissa */ 184 float24 |= (u.u & 0x7FFFFF) >> 7; 185 186 return float24; 187 } 188 189 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state) 190 { 191 struct r300_fragment_shader *fs = r300_fs(r300); 192 CS_LOCALS(r300); 193 194 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size); 195 } 196 197 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state) 198 { 199 struct r300_fragment_shader *fs = r300_fs(r300); 200 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state; 201 unsigned count = fs->shader->externals_count; 202 unsigned i, j; 203 CS_LOCALS(r300); 204 205 if (count == 0) 206 return; 207 208 BEGIN_CS(size); 209 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4); 210 if (buf->remap_table){ 211 for (i = 0; i < count; i++) { 212 float *data = (float*)&buf->ptr[buf->remap_table[i]*4]; 213 for (j = 0; j < 4; j++) 214 OUT_CS(pack_float24(data[j])); 215 } 216 } else { 217 for (i = 0; i < count; i++) 218 for (j = 0; j < 4; j++) 219 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j])); 220 } 221 222 END_CS; 223 } 224 225 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state) 226 { 227 struct r300_fragment_shader *fs = r300_fs(r300); 228 struct rc_constant_list *constants = &fs->shader->code.constants; 229 unsigned i; 230 unsigned count = fs->shader->rc_state_count; 231 unsigned first = fs->shader->externals_count; 232 unsigned end = constants->Count; 233 unsigned j; 234 CS_LOCALS(r300); 235 236 if (count == 0) 237 return; 238 239 BEGIN_CS(size); 240 for(i = first; i < end; ++i) { 241 if (constants->Constants[i].Type == RC_CONSTANT_STATE) { 242 float data[4]; 243 244 get_rc_constant_state(data, r300, &constants->Constants[i]); 245 246 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4); 247 for (j = 0; j < 4; j++) 248 OUT_CS(pack_float24(data[j])); 249 } 250 } 251 END_CS; 252 } 253 254 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state) 255 { 256 struct r300_fragment_shader *fs = r300_fs(r300); 257 CS_LOCALS(r300); 258 259 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size); 260 } 261 262 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state) 263 { 264 struct r300_fragment_shader *fs = r300_fs(r300); 265 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state; 266 unsigned count = fs->shader->externals_count; 267 CS_LOCALS(r300); 268 269 if (count == 0) 270 return; 271 272 BEGIN_CS(size); 273 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST); 274 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4); 275 if (buf->remap_table){ 276 for (unsigned i = 0; i < count; i++) { 277 uint32_t *data = &buf->ptr[buf->remap_table[i]*4]; 278 OUT_CS_TABLE(data, 4); 279 } 280 } else { 281 OUT_CS_TABLE(buf->ptr, count * 4); 282 } 283 END_CS; 284 } 285 286 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state) 287 { 288 struct r300_fragment_shader *fs = r300_fs(r300); 289 struct rc_constant_list *constants = &fs->shader->code.constants; 290 unsigned i; 291 unsigned count = fs->shader->rc_state_count; 292 unsigned first = fs->shader->externals_count; 293 unsigned end = constants->Count; 294 CS_LOCALS(r300); 295 296 if (count == 0) 297 return; 298 299 BEGIN_CS(size); 300 for(i = first; i < end; ++i) { 301 if (constants->Constants[i].Type == RC_CONSTANT_STATE) { 302 float data[4]; 303 304 get_rc_constant_state(data, r300, &constants->Constants[i]); 305 306 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, 307 R500_GA_US_VECTOR_INDEX_TYPE_CONST | 308 (i & R500_GA_US_VECTOR_INDEX_MASK)); 309 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4); 310 OUT_CS_TABLE(data, 4); 311 } 312 } 313 END_CS; 314 } 315 316 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state) 317 { 318 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state; 319 struct pipe_framebuffer_state* fb = 320 (struct pipe_framebuffer_state*)r300->fb_state.state; 321 uint32_t height = fb->height; 322 uint32_t width = fb->width; 323 CS_LOCALS(r300); 324 325 if (r300->cbzb_clear) { 326 struct r300_surface *surf = r300_surface(fb->cbufs[0]); 327 328 height = surf->cbzb_height; 329 width = surf->cbzb_width; 330 } 331 332 DBG(r300, DBG_SCISSOR, 333 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n", 334 width, height, r300->cbzb_clear ? "YES" : "NO"); 335 336 BEGIN_CS(size); 337 338 /* Set up scissors. 339 * By writing to the SC registers, SC & US assert idle. */ 340 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2); 341 if (r300->screen->caps.is_r500) { 342 OUT_CS(0); 343 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) | 344 ((height - 1) << R300_SCISSORS_Y_SHIFT)); 345 } else { 346 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) | 347 (1440 << R300_SCISSORS_Y_SHIFT)); 348 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) | 349 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT)); 350 } 351 352 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */ 353 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6); 354 END_CS; 355 } 356 357 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state) 358 { 359 struct r300_aa_state *aa = (struct r300_aa_state*)state; 360 CS_LOCALS(r300); 361 362 BEGIN_CS(size); 363 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config); 364 365 if (aa->dest) { 366 OUT_CS_REG(R300_RB3D_AARESOLVE_OFFSET, aa->dest->offset); 367 OUT_CS_RELOC(aa->dest); 368 OUT_CS_REG(R300_RB3D_AARESOLVE_PITCH, aa->dest->pitch); 369 } 370 371 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl); 372 END_CS; 373 } 374 375 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state) 376 { 377 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state; 378 struct r300_surface* surf; 379 unsigned i; 380 uint32_t rb3d_cctl = 0; 381 382 CS_LOCALS(r300); 383 384 BEGIN_CS(size); 385 386 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not 387 * what we usually want. */ 388 if (r300->screen->caps.is_r500) { 389 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE; 390 } 391 if (fb->nr_cbufs && r300->fb_multiwrite) { 392 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs); 393 } 394 395 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl); 396 397 /* Set up colorbuffers. */ 398 for (i = 0; i < fb->nr_cbufs; i++) { 399 surf = r300_surface(fb->cbufs[i]); 400 401 OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset); 402 OUT_CS_RELOC(surf); 403 404 OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch); 405 OUT_CS_RELOC(surf); 406 } 407 408 /* Set up the ZB part of the CBZB clear. */ 409 if (r300->cbzb_clear) { 410 surf = r300_surface(fb->cbufs[0]); 411 412 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format); 413 414 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset); 415 OUT_CS_RELOC(surf); 416 417 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch); 418 OUT_CS_RELOC(surf); 419 420 DBG(r300, DBG_CBZB, 421 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format, 422 surf->cbzb_pitch); 423 } 424 /* Set up a zbuffer. */ 425 else if (fb->zsbuf) { 426 surf = r300_surface(fb->zsbuf); 427 428 OUT_CS_REG(R300_ZB_FORMAT, surf->format); 429 430 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset); 431 OUT_CS_RELOC(surf); 432 433 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch); 434 OUT_CS_RELOC(surf); 435 436 if (r300->hyperz_enabled) { 437 /* HiZ RAM. */ 438 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0); 439 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz); 440 /* Z Mask RAM. (compressed zbuffer) */ 441 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0); 442 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask); 443 } 444 /* Set up a dummy zbuffer. Otherwise occlusion queries won't work. 445 * Use the first colorbuffer, we will disable writes in the DSA state 446 * so as not to corrupt it. */ 447 } else if (fb->nr_cbufs) { 448 surf = r300_surface(fb->cbufs[0]); 449 450 OUT_CS_REG(R300_ZB_FORMAT, R300_DEPTHFORMAT_16BIT_INT_Z); 451 452 OUT_CS_REG(R300_ZB_DEPTHOFFSET, 0); 453 OUT_CS_RELOC(surf); 454 455 OUT_CS_REG(R300_ZB_DEPTHPITCH, 4 | R300_DEPTHMICROTILE_TILED_SQUARE); 456 OUT_CS_RELOC(surf); 457 } 458 459 END_CS; 460 } 461 462 void r300_emit_hyperz_state(struct r300_context *r300, 463 unsigned size, void *state) 464 { 465 struct r300_hyperz_state *z = state; 466 CS_LOCALS(r300); 467 468 if (z->flush) 469 WRITE_CS_TABLE(&z->cb_flush_begin, size); 470 else 471 WRITE_CS_TABLE(&z->cb_begin, size - 2); 472 } 473 474 void r300_emit_hyperz_end(struct r300_context *r300) 475 { 476 struct r300_hyperz_state z = 477 *(struct r300_hyperz_state*)r300->hyperz_state.state; 478 479 z.flush = 1; 480 z.zb_bw_cntl = 0; 481 z.zb_depthclearvalue = 0; 482 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2; 483 z.gb_z_peq_config = 0; 484 485 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z); 486 } 487 488 void r300_emit_fb_state_pipelined(struct r300_context *r300, 489 unsigned size, void *state) 490 { 491 struct pipe_framebuffer_state* fb = 492 (struct pipe_framebuffer_state*)r300->fb_state.state; 493 unsigned i, num_cbufs = fb->nr_cbufs; 494 unsigned mspos0, mspos1; 495 CS_LOCALS(r300); 496 497 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be 498 * marked as UNUSED in the US block. */ 499 if (r300->fb_multiwrite) { 500 num_cbufs = MIN2(num_cbufs, 1); 501 } 502 503 BEGIN_CS(size); 504 505 /* Colorbuffer format in the US block. 506 * (must be written after unpipelined regs) */ 507 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4); 508 for (i = 0; i < num_cbufs; i++) { 509 OUT_CS(r300_surface(fb->cbufs[i])->format); 510 } 511 for (; i < 1; i++) { 512 OUT_CS(R300_US_OUT_FMT_C4_8 | 513 R300_C0_SEL_B | R300_C1_SEL_G | 514 R300_C2_SEL_R | R300_C3_SEL_A); 515 } 516 for (; i < 4; i++) { 517 OUT_CS(R300_US_OUT_FMT_UNUSED); 518 } 519 520 /* Multisampling. Depends on framebuffer sample count. 521 * These are pipelined regs and as such cannot be moved 522 * to the AA state. */ 523 mspos0 = 0x66666666; 524 mspos1 = 0x6666666; 525 526 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) { 527 /* Subsample placement. These may not be optimal. */ 528 switch (fb->cbufs[0]->texture->nr_samples) { 529 case 2: 530 mspos0 = 0x33996633; 531 mspos1 = 0x6666663; 532 break; 533 case 3: 534 mspos0 = 0x33936933; 535 mspos1 = 0x6666663; 536 break; 537 case 4: 538 mspos0 = 0x33939933; 539 mspos1 = 0x3966663; 540 break; 541 case 6: 542 mspos0 = 0x22a2aa22; 543 mspos1 = 0x2a65672; 544 break; 545 default: 546 debug_printf("r300: Bad number of multisamples!\n"); 547 } 548 } 549 550 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2); 551 OUT_CS(mspos0); 552 OUT_CS(mspos1); 553 END_CS; 554 } 555 556 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state) 557 { 558 struct r300_query *query = r300->query_current; 559 CS_LOCALS(r300); 560 561 if (!query) 562 return; 563 564 BEGIN_CS(size); 565 if (r300->screen->caps.family == CHIP_FAMILY_RV530) { 566 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); 567 } else { 568 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL); 569 } 570 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0); 571 END_CS; 572 query->begin_emitted = TRUE; 573 } 574 575 static void r300_emit_query_end_frag_pipes(struct r300_context *r300, 576 struct r300_query *query) 577 { 578 struct r300_capabilities* caps = &r300->screen->caps; 579 uint32_t gb_pipes = r300->screen->info.r300_num_gb_pipes; 580 CS_LOCALS(r300); 581 582 assert(gb_pipes); 583 584 BEGIN_CS(6 * gb_pipes + 2); 585 /* I'm not so sure I like this switch, but it's hard to be elegant 586 * when there's so many special cases... 587 * 588 * So here's the basic idea. For each pipe, enable writes to it only, 589 * then put out the relocation for ZPASS_ADDR, taking into account a 590 * 4-byte offset for each pipe. RV380 and older are special; they have 591 * only two pipes, and the second pipe's enable is on bit 3, not bit 1, 592 * so there's a chipset cap for that. */ 593 switch (gb_pipes) { 594 case 4: 595 /* pipe 3 only */ 596 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3); 597 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4); 598 OUT_CS_RELOC(r300->query_current); 599 case 3: 600 /* pipe 2 only */ 601 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2); 602 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4); 603 OUT_CS_RELOC(r300->query_current); 604 case 2: 605 /* pipe 1 only */ 606 /* As mentioned above, accomodate RV380 and older. */ 607 OUT_CS_REG(R300_SU_REG_DEST, 608 1 << (caps->high_second_pipe ? 3 : 1)); 609 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4); 610 OUT_CS_RELOC(r300->query_current); 611 case 1: 612 /* pipe 0 only */ 613 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0); 614 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4); 615 OUT_CS_RELOC(r300->query_current); 616 break; 617 default: 618 fprintf(stderr, "r300: Implementation error: Chipset reports %d" 619 " pixel pipes!\n", gb_pipes); 620 abort(); 621 } 622 623 /* And, finally, reset it to normal... */ 624 OUT_CS_REG(R300_SU_REG_DEST, 0xF); 625 END_CS; 626 } 627 628 static void rv530_emit_query_end_single_z(struct r300_context *r300, 629 struct r300_query *query) 630 { 631 CS_LOCALS(r300); 632 633 BEGIN_CS(8); 634 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0); 635 OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4); 636 OUT_CS_RELOC(r300->query_current); 637 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); 638 END_CS; 639 } 640 641 static void rv530_emit_query_end_double_z(struct r300_context *r300, 642 struct r300_query *query) 643 { 644 CS_LOCALS(r300); 645 646 BEGIN_CS(14); 647 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0); 648 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4); 649 OUT_CS_RELOC(r300->query_current); 650 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1); 651 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4); 652 OUT_CS_RELOC(r300->query_current); 653 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); 654 END_CS; 655 } 656 657 void r300_emit_query_end(struct r300_context* r300) 658 { 659 struct r300_capabilities *caps = &r300->screen->caps; 660 struct r300_query *query = r300->query_current; 661 662 if (!query) 663 return; 664 665 if (query->begin_emitted == FALSE) 666 return; 667 668 if (caps->family == CHIP_FAMILY_RV530) { 669 if (r300->screen->info.r300_num_z_pipes == 2) 670 rv530_emit_query_end_double_z(r300, query); 671 else 672 rv530_emit_query_end_single_z(r300, query); 673 } else 674 r300_emit_query_end_frag_pipes(r300, query); 675 676 query->begin_emitted = FALSE; 677 query->num_results += query->num_pipes; 678 679 /* XXX grab all the results and reset the counter. */ 680 if (query->num_results >= query->buf->size / 4 - 4) { 681 query->num_results = (query->buf->size / 4) / 2; 682 fprintf(stderr, "r300: Rewinding OQBO...\n"); 683 } 684 } 685 686 void r300_emit_invariant_state(struct r300_context *r300, 687 unsigned size, void *state) 688 { 689 CS_LOCALS(r300); 690 WRITE_CS_TABLE(state, size); 691 } 692 693 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state) 694 { 695 struct r300_rs_state* rs = state; 696 CS_LOCALS(r300); 697 698 BEGIN_CS(size); 699 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE); 700 if (rs->polygon_offset_enable) { 701 if (r300->zbuffer_bpp == 16) { 702 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5); 703 } else { 704 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5); 705 } 706 } 707 END_CS; 708 } 709 710 void r300_emit_rs_block_state(struct r300_context* r300, 711 unsigned size, void* state) 712 { 713 struct r300_rs_block* rs = (struct r300_rs_block*)state; 714 unsigned i; 715 /* It's the same for both INST and IP tables */ 716 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1; 717 CS_LOCALS(r300); 718 719 if (DBG_ON(r300, DBG_RS_BLOCK)) { 720 r500_dump_rs_block(rs); 721 722 fprintf(stderr, "r300: RS emit:\n"); 723 724 for (i = 0; i < count; i++) 725 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]); 726 727 for (i = 0; i < count; i++) 728 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]); 729 730 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n", 731 rs->count, rs->inst_count); 732 } 733 734 BEGIN_CS(size); 735 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2); 736 OUT_CS(rs->vap_vtx_state_cntl); 737 OUT_CS(rs->vap_vsm_vtx_assm); 738 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2); 739 OUT_CS(rs->vap_out_vtx_fmt[0]); 740 OUT_CS(rs->vap_out_vtx_fmt[1]); 741 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1); 742 OUT_CS(rs->gb_enable); 743 744 if (r300->screen->caps.is_r500) { 745 OUT_CS_REG_SEQ(R500_RS_IP_0, count); 746 } else { 747 OUT_CS_REG_SEQ(R300_RS_IP_0, count); 748 } 749 OUT_CS_TABLE(rs->ip, count); 750 751 OUT_CS_REG_SEQ(R300_RS_COUNT, 2); 752 OUT_CS(rs->count); 753 OUT_CS(rs->inst_count); 754 755 if (r300->screen->caps.is_r500) { 756 OUT_CS_REG_SEQ(R500_RS_INST_0, count); 757 } else { 758 OUT_CS_REG_SEQ(R300_RS_INST_0, count); 759 } 760 OUT_CS_TABLE(rs->inst, count); 761 END_CS; 762 } 763 764 void r300_emit_scissor_state(struct r300_context* r300, 765 unsigned size, void* state) 766 { 767 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state; 768 CS_LOCALS(r300); 769 770 BEGIN_CS(size); 771 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2); 772 if (r300->screen->caps.is_r500) { 773 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) | 774 (scissor->miny << R300_CLIPRECT_Y_SHIFT)); 775 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) | 776 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT)); 777 } else { 778 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) | 779 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT)); 780 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) | 781 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT)); 782 } 783 END_CS; 784 } 785 786 void r300_emit_textures_state(struct r300_context *r300, 787 unsigned size, void *state) 788 { 789 struct r300_textures_state *allstate = (struct r300_textures_state*)state; 790 struct r300_texture_sampler_state *texstate; 791 struct r300_resource *tex; 792 unsigned i; 793 boolean has_us_format = r300->screen->caps.has_us_format; 794 CS_LOCALS(r300); 795 796 BEGIN_CS(size); 797 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable); 798 799 for (i = 0; i < allstate->count; i++) { 800 if ((1 << i) & allstate->tx_enable) { 801 texstate = &allstate->regs[i]; 802 tex = r300_resource(allstate->sampler_views[i]->base.texture); 803 804 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0); 805 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1); 806 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4), 807 texstate->border_color); 808 809 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0); 810 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1); 811 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2); 812 813 OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config); 814 OUT_CS_RELOC(tex); 815 816 if (has_us_format) { 817 OUT_CS_REG(R500_US_FORMAT0_0 + (i * 4), 818 texstate->format.us_format0); 819 } 820 } 821 } 822 END_CS; 823 } 824 825 void r300_emit_vertex_arrays(struct r300_context* r300, int offset, 826 boolean indexed, int instance_id) 827 { 828 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer; 829 struct pipe_vertex_element *velem = r300->velems->velem; 830 struct r300_resource *buf; 831 int i; 832 unsigned vertex_array_count = r300->velems->count; 833 unsigned packet_size = (vertex_array_count * 3 + 1) / 2; 834 struct pipe_vertex_buffer *vb1, *vb2; 835 unsigned *hw_format_size = r300->velems->format_size; 836 unsigned size1, size2, offset1, offset2, stride1, stride2; 837 CS_LOCALS(r300); 838 839 BEGIN_CS(2 + packet_size + vertex_array_count * 2); 840 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size); 841 OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0)); 842 843 if (instance_id == -1) { 844 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */ 845 for (i = 0; i < vertex_array_count - 1; i += 2) { 846 vb1 = &vbuf[velem[i].vertex_buffer_index]; 847 vb2 = &vbuf[velem[i+1].vertex_buffer_index]; 848 size1 = hw_format_size[i]; 849 size2 = hw_format_size[i+1]; 850 851 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) | 852 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride)); 853 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride); 854 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride); 855 } 856 857 if (vertex_array_count & 1) { 858 vb1 = &vbuf[velem[i].vertex_buffer_index]; 859 size1 = hw_format_size[i]; 860 861 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride)); 862 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride); 863 } 864 865 for (i = 0; i < vertex_array_count; i++) { 866 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer); 867 OUT_CS_RELOC(buf); 868 } 869 } else { 870 /* Instanced arrays. */ 871 for (i = 0; i < vertex_array_count - 1; i += 2) { 872 vb1 = &vbuf[velem[i].vertex_buffer_index]; 873 vb2 = &vbuf[velem[i+1].vertex_buffer_index]; 874 size1 = hw_format_size[i]; 875 size2 = hw_format_size[i+1]; 876 877 if (velem[i].instance_divisor) { 878 stride1 = 0; 879 offset1 = vb1->buffer_offset + velem[i].src_offset + 880 (instance_id / velem[i].instance_divisor) * vb1->stride; 881 } else { 882 stride1 = vb1->stride; 883 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride; 884 } 885 if (velem[i+1].instance_divisor) { 886 stride2 = 0; 887 offset2 = vb2->buffer_offset + velem[i+1].src_offset + 888 (instance_id / velem[i+1].instance_divisor) * vb2->stride; 889 } else { 890 stride2 = vb2->stride; 891 offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride; 892 } 893 894 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) | 895 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2)); 896 OUT_CS(offset1); 897 OUT_CS(offset2); 898 } 899 900 if (vertex_array_count & 1) { 901 vb1 = &vbuf[velem[i].vertex_buffer_index]; 902 size1 = hw_format_size[i]; 903 904 if (velem[i].instance_divisor) { 905 stride1 = 0; 906 offset1 = vb1->buffer_offset + velem[i].src_offset + 907 (instance_id / velem[i].instance_divisor) * vb1->stride; 908 } else { 909 stride1 = vb1->stride; 910 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride; 911 } 912 913 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1)); 914 OUT_CS(offset1); 915 } 916 917 for (i = 0; i < vertex_array_count; i++) { 918 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer); 919 OUT_CS_RELOC(buf); 920 } 921 } 922 END_CS; 923 } 924 925 void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed) 926 { 927 CS_LOCALS(r300); 928 929 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, " 930 "vertex size %d\n", r300->vbo, 931 r300->vertex_info.size); 932 /* Set the pointer to our vertex buffer. The emitted values are this: 933 * PACKET3 [3D_LOAD_VBPNTR] 934 * COUNT [1] 935 * FORMAT [size | stride << 8] 936 * OFFSET [offset into BO] 937 * VBPNTR [relocated BO] 938 */ 939 BEGIN_CS(7); 940 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3); 941 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0)); 942 OUT_CS(r300->vertex_info.size | 943 (r300->vertex_info.size << 8)); 944 OUT_CS(r300->draw_vbo_offset); 945 OUT_CS(0); 946 OUT_CS_RELOC(r300_resource(r300->vbo)); 947 END_CS; 948 } 949 950 void r300_emit_vertex_stream_state(struct r300_context* r300, 951 unsigned size, void* state) 952 { 953 struct r300_vertex_stream_state *streams = 954 (struct r300_vertex_stream_state*)state; 955 unsigned i; 956 CS_LOCALS(r300); 957 958 if (DBG_ON(r300, DBG_PSC)) { 959 fprintf(stderr, "r300: PSC emit:\n"); 960 961 for (i = 0; i < streams->count; i++) { 962 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i, 963 streams->vap_prog_stream_cntl[i]); 964 } 965 966 for (i = 0; i < streams->count; i++) { 967 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i, 968 streams->vap_prog_stream_cntl_ext[i]); 969 } 970 } 971 972 BEGIN_CS(size); 973 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count); 974 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count); 975 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count); 976 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count); 977 END_CS; 978 } 979 980 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state) 981 { 982 CS_LOCALS(r300); 983 984 BEGIN_CS(size); 985 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); 986 END_CS; 987 } 988 989 void r300_emit_vap_invariant_state(struct r300_context *r300, 990 unsigned size, void *state) 991 { 992 CS_LOCALS(r300); 993 WRITE_CS_TABLE(state, size); 994 } 995 996 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state) 997 { 998 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state; 999 struct r300_vertex_program_code* code = &vs->code; 1000 struct r300_screen* r300screen = r300->screen; 1001 unsigned instruction_count = code->length / 4; 1002 1003 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72; 1004 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1); 1005 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1); 1006 unsigned temp_count = MAX2(code->num_temporaries, 1); 1007 1008 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count, 1009 vtx_mem_size / output_count, 10); 1010 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5); 1011 1012 CS_LOCALS(r300); 1013 1014 BEGIN_CS(size); 1015 1016 /* R300_VAP_PVS_CODE_CNTL_0 1017 * R300_VAP_PVS_CONST_CNTL 1018 * R300_VAP_PVS_CODE_CNTL_1 1019 * See the r5xx docs for instructions on how to use these. */ 1020 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) | 1021 R300_PVS_XYZW_VALID_INST(instruction_count - 1) | 1022 R300_PVS_LAST_INST(instruction_count - 1)); 1023 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1); 1024 1025 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); 1026 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length); 1027 OUT_CS_TABLE(code->body.d, code->length); 1028 1029 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) | 1030 R300_PVS_NUM_CNTLRS(pvs_num_controllers) | 1031 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) | 1032 R300_PVS_VF_MAX_VTX_NUM(12) | 1033 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0)); 1034 1035 /* Emit flow control instructions. Even if there are no fc instructions, 1036 * we still need to write the registers to make sure they are cleared. */ 1037 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops); 1038 if (r300screen->caps.is_r500) { 1039 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, R300_VS_MAX_FC_OPS * 2); 1040 OUT_CS_TABLE(code->fc_op_addrs.r500, R300_VS_MAX_FC_OPS * 2); 1041 } else { 1042 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, R300_VS_MAX_FC_OPS); 1043 OUT_CS_TABLE(code->fc_op_addrs.r300, R300_VS_MAX_FC_OPS); 1044 } 1045 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, R300_VS_MAX_FC_OPS); 1046 OUT_CS_TABLE(code->fc_loop_index, R300_VS_MAX_FC_OPS); 1047 1048 END_CS; 1049 } 1050 1051 void r300_emit_vs_constants(struct r300_context* r300, 1052 unsigned size, void *state) 1053 { 1054 unsigned count = 1055 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count; 1056 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state; 1057 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state; 1058 unsigned i; 1059 int imm_first = vs->externals_count; 1060 int imm_end = vs->code.constants.Count; 1061 int imm_count = vs->immediates_count; 1062 CS_LOCALS(r300); 1063 1064 BEGIN_CS(size); 1065 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 1066 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) | 1067 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0))); 1068 if (vs->externals_count) { 1069 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 1070 (r300->screen->caps.is_r500 ? 1071 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base); 1072 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4); 1073 if (buf->remap_table){ 1074 for (i = 0; i < count; i++) { 1075 uint32_t *data = &buf->ptr[buf->remap_table[i]*4]; 1076 OUT_CS_TABLE(data, 4); 1077 } 1078 } else { 1079 OUT_CS_TABLE(buf->ptr, count * 4); 1080 } 1081 } 1082 1083 /* Emit immediates. */ 1084 if (imm_count) { 1085 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 1086 (r300->screen->caps.is_r500 ? 1087 R500_PVS_CONST_START : R300_PVS_CONST_START) + 1088 buf->buffer_base + imm_first); 1089 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4); 1090 for (i = imm_first; i < imm_end; i++) { 1091 const float *data = vs->code.constants.Constants[i].u.Immediate; 1092 OUT_CS_TABLE(data, 4); 1093 } 1094 } 1095 END_CS; 1096 } 1097 1098 void r300_emit_viewport_state(struct r300_context* r300, 1099 unsigned size, void* state) 1100 { 1101 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state; 1102 CS_LOCALS(r300); 1103 1104 BEGIN_CS(size); 1105 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6); 1106 OUT_CS_TABLE(&viewport->xscale, 6); 1107 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control); 1108 END_CS; 1109 } 1110 1111 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state) 1112 { 1113 struct pipe_framebuffer_state *fb = 1114 (struct pipe_framebuffer_state*)r300->fb_state.state; 1115 struct r300_resource* tex; 1116 CS_LOCALS(r300); 1117 1118 tex = r300_resource(fb->zsbuf->texture); 1119 1120 BEGIN_CS(size); 1121 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2); 1122 OUT_CS(0); 1123 OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]); 1124 OUT_CS(r300->hiz_clear_value); 1125 END_CS; 1126 1127 /* Mark the current zbuffer's hiz ram as in use. */ 1128 r300->hiz_in_use = TRUE; 1129 r300->hiz_func = HIZ_FUNC_NONE; 1130 r300_mark_atom_dirty(r300, &r300->hyperz_state); 1131 } 1132 1133 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state) 1134 { 1135 struct pipe_framebuffer_state *fb = 1136 (struct pipe_framebuffer_state*)r300->fb_state.state; 1137 struct r300_resource *tex; 1138 CS_LOCALS(r300); 1139 1140 tex = r300_resource(fb->zsbuf->texture); 1141 1142 BEGIN_CS(size); 1143 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2); 1144 OUT_CS(0); 1145 OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]); 1146 OUT_CS(0); 1147 END_CS; 1148 1149 /* Mark the current zbuffer's zmask as in use. */ 1150 r300->zmask_in_use = TRUE; 1151 r300_mark_atom_dirty(r300, &r300->hyperz_state); 1152 } 1153 1154 void r300_emit_ztop_state(struct r300_context* r300, 1155 unsigned size, void* state) 1156 { 1157 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state; 1158 CS_LOCALS(r300); 1159 1160 BEGIN_CS(size); 1161 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top); 1162 END_CS; 1163 } 1164 1165 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state) 1166 { 1167 CS_LOCALS(r300); 1168 1169 BEGIN_CS(size); 1170 OUT_CS_REG(R300_TX_INVALTAGS, 0); 1171 END_CS; 1172 } 1173 1174 boolean r300_emit_buffer_validate(struct r300_context *r300, 1175 boolean do_validate_vertex_buffers, 1176 struct pipe_resource *index_buffer) 1177 { 1178 struct pipe_framebuffer_state *fb = 1179 (struct pipe_framebuffer_state*)r300->fb_state.state; 1180 struct r300_textures_state *texstate = 1181 (struct r300_textures_state*)r300->textures_state.state; 1182 struct r300_resource *tex; 1183 unsigned i; 1184 boolean flushed = FALSE; 1185 1186 validate: 1187 if (r300->fb_state.dirty) { 1188 /* Color buffers... */ 1189 for (i = 0; i < fb->nr_cbufs; i++) { 1190 tex = r300_resource(fb->cbufs[i]->texture); 1191 assert(tex && tex->buf && "cbuf is marked, but NULL!"); 1192 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, 1193 RADEON_USAGE_READWRITE, 1194 r300_surface(fb->cbufs[i])->domain); 1195 } 1196 /* ...depth buffer... */ 1197 if (fb->zsbuf) { 1198 tex = r300_resource(fb->zsbuf->texture); 1199 assert(tex && tex->buf && "zsbuf is marked, but NULL!"); 1200 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, 1201 RADEON_USAGE_READWRITE, 1202 r300_surface(fb->zsbuf)->domain); 1203 } 1204 } 1205 if (r300->textures_state.dirty) { 1206 /* ...textures... */ 1207 for (i = 0; i < texstate->count; i++) { 1208 if (!(texstate->tx_enable & (1 << i))) { 1209 continue; 1210 } 1211 1212 tex = r300_resource(texstate->sampler_views[i]->base.texture); 1213 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, RADEON_USAGE_READ, 1214 tex->domain); 1215 } 1216 } 1217 /* ...occlusion query buffer... */ 1218 if (r300->query_current) 1219 r300->rws->cs_add_reloc(r300->cs, r300->query_current->cs_buf, 1220 RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT); 1221 /* ...vertex buffer for SWTCL path... */ 1222 if (r300->vbo) 1223 r300->rws->cs_add_reloc(r300->cs, r300_resource(r300->vbo)->cs_buf, 1224 RADEON_USAGE_READ, 1225 r300_resource(r300->vbo)->domain); 1226 /* ...vertex buffers for HWTCL path... */ 1227 if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) { 1228 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer; 1229 struct pipe_vertex_buffer *last = r300->vertex_buffer + 1230 r300->nr_vertex_buffers; 1231 struct pipe_resource *buf; 1232 1233 for (; vbuf != last; vbuf++) { 1234 buf = vbuf->buffer; 1235 if (!buf) 1236 continue; 1237 1238 r300->rws->cs_add_reloc(r300->cs, r300_resource(buf)->cs_buf, 1239 RADEON_USAGE_READ, 1240 r300_resource(buf)->domain); 1241 } 1242 } 1243 /* ...and index buffer for HWTCL path. */ 1244 if (index_buffer) 1245 r300->rws->cs_add_reloc(r300->cs, r300_resource(index_buffer)->cs_buf, 1246 RADEON_USAGE_READ, 1247 r300_resource(index_buffer)->domain); 1248 1249 /* Now do the validation (flush is called inside cs_validate on failure). */ 1250 if (!r300->rws->cs_validate(r300->cs)) { 1251 /* Ooops, an infinite loop, give up. */ 1252 if (flushed) 1253 return FALSE; 1254 1255 flushed = TRUE; 1256 goto validate; 1257 } 1258 1259 return TRUE; 1260 } 1261 1262 unsigned r300_get_num_dirty_dwords(struct r300_context *r300) 1263 { 1264 struct r300_atom* atom; 1265 unsigned dwords = 0; 1266 1267 foreach_dirty_atom(r300, atom) { 1268 if (atom->dirty) { 1269 dwords += atom->size; 1270 } 1271 } 1272 1273 /* let's reserve some more, just in case */ 1274 dwords += 32; 1275 1276 return dwords; 1277 } 1278 1279 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300) 1280 { 1281 unsigned dwords = 0; 1282 1283 /* Emitted in flush. */ 1284 dwords += 26; /* emit_query_end */ 1285 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */ 1286 if (r300->screen->caps.is_r500) 1287 dwords += 2; 1288 1289 return dwords; 1290 } 1291 1292 /* Emit all dirty state. */ 1293 void r300_emit_dirty_state(struct r300_context* r300) 1294 { 1295 struct r300_atom *atom; 1296 1297 foreach_dirty_atom(r300, atom) { 1298 if (atom->dirty) { 1299 atom->emit(r300, atom->size, atom->state); 1300 atom->dirty = FALSE; 1301 } 1302 } 1303 1304 r300->first_dirty = NULL; 1305 r300->last_dirty = NULL; 1306 r300->dirty_hw++; 1307 } 1308
