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      1 /****************************************************************************
      2  ****************************************************************************
      3  ***
      4  ***   This header was automatically generated from a Linux kernel header
      5  ***   of the same name, to make information necessary for userspace to
      6  ***   call into the kernel available to libc.  It contains only constants,
      7  ***   structures, and macros generated from the original header, and thus,
      8  ***   contains no copyrightable information.
      9  ***
     10  ***   To edit the content of this header, modify the corresponding
     11  ***   source file (e.g. under external/kernel-headers/original/) then
     12  ***   run bionic/libc/kernel/tools/update_all.py
     13  ***
     14  ***   Any manual change here will be lost the next time this script will
     15  ***   be run. You've been warned!
     16  ***
     17  ****************************************************************************
     18  ****************************************************************************/
     19 #ifndef _ASM_IO_H
     20 #define _ASM_IO_H
     21 #include <linux/compiler.h>
     22 #include <linux/kernel.h>
     23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     24 #include <linux/types.h>
     25 #include <asm/addrspace.h>
     26 #include <asm/byteorder.h>
     27 #include <asm/cpu.h>
     28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     29 #include <asm/cpu-features.h>
     30 #include <asm-generic/iomap.h>
     31 #include <asm/page.h>
     32 #include <asm/pgtable-bits.h>
     33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     34 #include <asm/processor.h>
     35 #include <asm/string.h>
     36 #include <ioremap.h>
     37 #include <mangle-port.h>
     38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     39 #undef CONF_SLOWDOWN_IO
     40 #define __raw_ioswabb(a, x) (x)
     41 #define __raw_ioswabw(a, x) (x)
     42 #define __raw_ioswabl(a, x) (x)
     43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     44 #define __raw_ioswabq(a, x) (x)
     45 #define ____raw_ioswabq(a, x) (x)
     46 #define IO_SPACE_LIMIT 0xffff
     47 #define __SLOW_DOWN_IO   __asm__ __volatile__(   "sb\t$0,0x80(%0)"   : : "r" (mips_io_port_base));
     48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     49 #ifdef CONF_SLOWDOWN_IO
     50 #ifdef REALLY_SLOW_IO
     51 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
     52 #else
     53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     54 #define SLOW_DOWN_IO __SLOW_DOWN_IO
     55 #endif
     56 #else
     57 #define SLOW_DOWN_IO
     58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     59 #endif
     60 #define isa_page_to_bus page_to_phys
     61 #define virt_to_bus virt_to_phys
     62 #define bus_to_virt phys_to_virt
     63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     64 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
     65 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
     66 #undef __IS_LOW512
     67 #define ioremap(offset, size)   __ioremap_mode((offset), (size), _CACHE_UNCACHED)
     68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     69 #define ioremap_nocache(offset, size)   __ioremap_mode((offset), (size), _CACHE_UNCACHED)
     70 #define ioremap_cachable(offset, size)   __ioremap_mode((offset), (size), _page_cachable_default)
     71 #define ioremap_cacheable_cow(offset, size)   __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
     72 #define ioremap_uncached_accelerated(offset, size)   __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
     73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     74 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
     75 #undef __IS_KSEG1
     76 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)    static inline void pfx##write##bwlq(type val,   volatile void __iomem *mem)  {   volatile type *__mem;   type __val;     __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));     __val = pfx##ioswab##bwlq(__mem, val);     if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long))   *__mem = __val;   else if (cpu_has_64bits) {   unsigned long __flags;   type __tmp;     if (irq)   local_irq_save(__flags);   __asm__ __volatile__(   ".set	mips3" "\t\t# __writeq""\n\t"   "dsll32	%L0, %L0, 0" "\n\t"   "dsrl32	%L0, %L0, 0" "\n\t"   "dsll32	%M0, %M0, 0" "\n\t"   "or	%L0, %L0, %M0" "\n\t"   "sd	%L0, %2" "\n\t"   ".set	mips0" "\n"   : "=r" (__tmp)   : "0" (__val), "m" (*__mem));   if (irq)   local_irq_restore(__flags);   } else   BUG();  }    static inline type pfx##read##bwlq(const volatile void __iomem *mem)  {   volatile type *__mem;   type __val;     __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));     if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long))   __val = *__mem;   else if (cpu_has_64bits) {   unsigned long __flags;     if (irq)   local_irq_save(__flags);   __asm__ __volatile__(   ".set	mips3" "\t\t# __readq" "\n\t"   "ld	%L0, %1" "\n\t"   "dsra32	%M0, %L0, 0" "\n\t"   "sll	%L0, %L0, 0" "\n\t"   ".set	mips0" "\n"   : "=r" (__val)   : "m" (*__mem));   if (irq)   local_irq_restore(__flags);   } else {   __val = 0;   BUG();   }     return pfx##ioswab##bwlq(__mem, __val);  }
     77 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)    static inline void pfx##out##bwlq##p(type val, unsigned long port)  {   volatile type *__addr;   type __val;     __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port);     __val = pfx##ioswab##bwlq(__addr, val);         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));     *__addr = __val;   slow;  }    static inline type pfx##in##bwlq##p(unsigned long port)  {   volatile type *__addr;   type __val;     __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port);     BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));     __val = *__addr;   slow;     return pfx##ioswab##bwlq(__addr, __val);  }
     78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     79 #define __BUILD_MEMORY_PFX(bus, bwlq, type)    __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
     80 #define BUILDIO_MEM(bwlq, type)    __BUILD_MEMORY_PFX(__raw_, bwlq, type)  __BUILD_MEMORY_PFX(, bwlq, type)  __BUILD_MEMORY_PFX(__mem_, bwlq, type)
     81 #define __BUILD_IOPORT_PFX(bus, bwlq, type)   __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)   __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
     82 #define BUILDIO_IOPORT(bwlq, type)   __BUILD_IOPORT_PFX(, bwlq, type)   __BUILD_IOPORT_PFX(__mem_, bwlq, type)
     83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     84 #define __BUILDIO(bwlq, type)    __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
     85 #define readb_relaxed readb
     86 #define readw_relaxed readw
     87 #define readl_relaxed readl
     88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     89 #define readq_relaxed readq
     90 #define readq readq
     91 #define writeq writeq
     92 #define __BUILD_MEMORY_STRING(bwlq, type)    static inline void writes##bwlq(volatile void __iomem *mem,   const void *addr, unsigned int count)  {   const volatile type *__addr = addr;     while (count--) {   __mem_write##bwlq(*__addr, mem);   __addr++;   }  }    static inline void reads##bwlq(volatile void __iomem *mem, void *addr,   unsigned int count)  {   volatile type *__addr = addr;     while (count--) {   *__addr = __mem_read##bwlq(mem);   __addr++;   }  }
     93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     94 #define __BUILD_IOPORT_STRING(bwlq, type)    static inline void outs##bwlq(unsigned long port, const void *addr,   unsigned int count)  {   const volatile type *__addr = addr;     while (count--) {   __mem_out##bwlq(*__addr, port);   __addr++;   }  }    static inline void ins##bwlq(unsigned long port, void *addr,   unsigned int count)  {   volatile type *__addr = addr;     while (count--) {   *__addr = __mem_in##bwlq(port);   __addr++;   }  }
     95 #define BUILDSTRING(bwlq, type)    __BUILD_MEMORY_STRING(bwlq, type)  __BUILD_IOPORT_STRING(bwlq, type)
     96 #define mmiowb() asm volatile ("sync" ::: "memory")
     97 #define dma_cache_wback_inv(start,size)   do { (void) (start); (void) (size); } while (0)
     98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
     99 #define dma_cache_wback(start,size)   do { (void) (start); (void) (size); } while (0)
    100 #define dma_cache_inv(start,size)   do { (void) (start); (void) (size); } while (0)
    101 #ifdef __MIPSEB__
    102 #define __CSR_32_ADJUST 4
    103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
    104 #else
    105 #define __CSR_32_ADJUST 0
    106 #endif
    107 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
    108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
    109 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
    110 #define xlate_dev_mem_ptr(p) __va(p)
    111 #define xlate_dev_kmem_ptr(p) p
    112 #endif
    113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
    114