Lines Matching defs:DefMI
1746 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1747 bool Invert = !DefMI;
1748 if (!DefMI)
1749 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1750 if (!DefMI)
1760 // Create a new predicated version of DefMI.
1763 DefMI->getDesc(), DestReg);
1765 // Copy all the DefMI operands, excluding its (null) predicate.
1766 const MCInstrDesc &DefDesc = DefMI->getDesc();
1769 NewMI.addOperand(DefMI->getOperand(i));
1778 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1790 // The caller will erase MI, but not DefMI.
1791 DefMI->eraseFromParent();
2491 MachineInstr *DefMI, unsigned Reg,
2494 unsigned DefOpc = DefMI->getOpcode();
2497 if (!DefMI->getOperand(1).isImm())
2504 const MCInstrDesc &DefMCID = DefMI->getDesc();
2507 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2509 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2510 // to delete DefMI.
2525 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2602 DefMI->eraseFromParent();
3317 const MachineInstr *DefMI,
3327 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3339 unsigned ShAmt = DefMI->getOperand(3).getImm();
3352 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3370 unsigned ShAmt = DefMI->getOperand(3).getImm();
3498 const MachineInstr *DefMI, unsigned DefIdx,
3505 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3507 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3511 if (DefMI->isBundle()) {
3512 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3513 DefMCID = &DefMI->getDesc();
3515 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3516 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3534 if (DefMI->getOpcode() == ARM::FMSTAT) {
3544 unsigned Latency = getInstrLatency(ItinData, DefMI);
3551 const MachineFunction *MF = DefMI->getParent()->getParent();
3563 unsigned DefAlign = DefMI->hasOneMemOperand()
3564 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3579 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3893 const MachineInstr *DefMI, unsigned DefIdx,
3895 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3903 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3905 Latency = getInstrLatency(ItinData, DefMI);
3914 const MachineInstr *DefMI, unsigned DefIdx) const {
3918 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3920 unsigned DefClass = DefMI->getDesc().getSchedClass();
