Lines Matching defs:Opcode
932 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
933 switch (Opcode) {
3386 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3393 // If we have an unordered opcode, we need to swap the operands to the VSEL
3736 default: llvm_unreachable("Invalid opcode!");
3766 default: llvm_unreachable("Invalid opcode!");
3790 default: llvm_unreachable("Invalid opcode!");
4226 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
5334 default: llvm_unreachable("Unknown shuffle opcode!");
5785 unsigned Opcode = N->getOpcode();
5786 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5796 unsigned Opcode = N->getOpcode();
5797 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6823 /// Return the load opcode for a given load size. If load size >= 8,
6824 /// neon opcode will be returned.
6842 /// Return the store opcode for a given store size. If store size >= 8,
6843 /// neon opcode will be returned.
6868 assert(LdOpc != 0 && "Should have a load opcode");
6900 assert(StOpc != 0 && "Should have a store opcode");
6969 // Select the correct opcode and register class for unit size load/store
7278 default: llvm_unreachable("unexpected opcode!");
7294 // true/false values to select between, and a branch opcode to use.
7403 // true/false values to select between, and a branch opcode to use.
7504 "converted opcode should be the same except for cc_out");
7866 // Figure out the right opcode.
8010 unsigned Opcode = N0.getOpcode();
8011 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8012 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8013 Opcode = N1.getOpcode();
8014 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8015 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8027 return DAG.getNode(Opcode, DL, VT,
8847 // Find the new opcode for the updating load/store.
8888 default: llvm_unreachable("unexpected opcode for Neon base update");
9226 /// operand of a vector shift right operation. For a shift opcode, the value
9324 // Opcode already set above.
9413 default: llvm_unreachable("unexpected shift opcode");
9457 default: llvm_unreachable("unexpected opcode");
9495 unsigned Opcode = 0;
9527 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9549 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9553 if (!Opcode)
9555 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
10553 unsigned Opcode = Op->getOpcode();
10554 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10555 "Invalid opcode for Div/Rem lowering");
10556 bool isSigned = (Opcode == ISD::SDIVREM);
