Lines Matching refs:Arg
1337 SDValue StackPtr, SDValue Arg,
1344 return DAG.getStore(Chain, dl, Arg, PtrOff,
1350 SDValue Chain, SDValue &Arg,
1358 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1450 SDValue Arg = OutVals[realArgIdx];
1459 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1462 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1465 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1468 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1475 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1477 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1494 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1505 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1524 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1546 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1559 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1847 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1850 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1852 if (Arg.getOpcode() == ISD::CopyFromReg) {
1853 unsigned VR = cast<RegisterSDNode>(Arg
1865 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2004 SDValue Arg = OutVals[realArgIdx];
2024 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2108 SDValue Arg = OutVals[realRVLocIdx];
2114 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2121 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2140 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2146 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2157 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2976 // If the arg regs save area contains N-byte aligned values, the
6083 SDValue Arg = Op.getOperand(0);
6084 EVT ArgVT = Arg.getValueType();
6109 Entry.Node = Arg;
