Lines Matching defs:Opcode
49 // each having the opcode given by NewOpcode.
141 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
143 MI->setDesc(get(Opcode));
167 unsigned Opcode;
171 Opcode = SystemZ::RISBHH;
173 Opcode = SystemZ::RISBHL;
175 Opcode = SystemZ::RISBLH;
182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
425 // Return true if MI is a shift of type Opcode by Imm bits.
426 static bool isShift(MachineInstr *MI, int Opcode, int64_t Imm) {
427 return (MI->getOpcode() == Opcode &&
496 // If Opcode is a move that has a conditional variant, return that variant,
498 static unsigned getConditionalMove(unsigned Opcode) {
499 switch (Opcode) {
507 unsigned Opcode = MI->getOpcode();
509 getConditionalMove(Opcode))
539 unsigned Opcode = MI->getOpcode();
541 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
572 unsigned Opcode;
574 Opcode = SystemZ::LGR;
576 Opcode = SystemZ::LER;
578 Opcode = SystemZ::LDR;
580 Opcode = SystemZ::LXR;
584 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
642 static LogicOp interpretAndImmediate(unsigned Opcode) {
643 switch (Opcode) {
681 unsigned Opcode = MI->getOpcode();
696 if (Opcode == SystemZ::AHIMux &&
704 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
719 if (LogicOp And = interpretAndImmediate(Opcode)) {
753 unsigned Opcode = MI->getOpcode();
756 if ((Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
776 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) &&
780 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
781 return BuildMI(MF, MI->getDebugLoc(), get(Opcode))
786 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
787 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
788 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
842 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1084 llvm_unreachable("Unrecognized branch opcode");
1121 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1123 const MCInstrDesc &MCID = get(Opcode);
1127 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1133 return Opcode;
1137 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1141 // Check whether Opcode allows signed 20-bit displacements.
1143 return Opcode;
1148 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1149 switch (Opcode) {
1206 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
1208 switch (Opcode) {
1234 unsigned Opcode;
1236 Opcode = SystemZ::LGHI;
1238 Opcode = SystemZ::LLILL;
1240 Opcode = SystemZ::LLILH;
1244 Opcode = SystemZ::LGFI;
1246 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
