1 //===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines an instruction selector for the NVPTX target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "NVPTX.h" 15 #include "NVPTXISelLowering.h" 16 #include "NVPTXRegisterInfo.h" 17 #include "NVPTXTargetMachine.h" 18 #include "llvm/CodeGen/SelectionDAGISel.h" 19 #include "llvm/IR/Intrinsics.h" 20 #include "llvm/Support/Compiler.h" 21 using namespace llvm; 22 23 namespace { 24 25 class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel { 26 27 // If true, generate corresponding FPCONTRACT. This is 28 // language dependent (i.e. CUDA and OpenCL works differently). 29 bool doFMAF64; 30 bool doFMAF32; 31 bool doFMAF64AGG; 32 bool doFMAF32AGG; 33 bool allowFMA; 34 35 // If true, generate mul.wide from sext and mul 36 bool doMulWide; 37 38 int getDivF32Level() const; 39 bool usePrecSqrtF32() const; 40 bool useF32FTZ() const; 41 42 public: 43 explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, 44 CodeGenOpt::Level OptLevel); 45 46 // Pass Name 47 const char *getPassName() const override { 48 return "NVPTX DAG->DAG Pattern Instruction Selection"; 49 } 50 51 const NVPTXSubtarget &Subtarget; 52 53 bool SelectInlineAsmMemoryOperand(const SDValue &Op, 54 char ConstraintCode, 55 std::vector<SDValue> &OutOps) override; 56 private: 57 // Include the pieces autogenerated from the target description. 58 #include "NVPTXGenDAGISel.inc" 59 60 SDNode *Select(SDNode *N) override; 61 SDNode *SelectIntrinsicNoChain(SDNode *N); 62 SDNode *SelectIntrinsicChain(SDNode *N); 63 SDNode *SelectTexSurfHandle(SDNode *N); 64 SDNode *SelectLoad(SDNode *N); 65 SDNode *SelectLoadVector(SDNode *N); 66 SDNode *SelectLDGLDU(SDNode *N); 67 SDNode *SelectStore(SDNode *N); 68 SDNode *SelectStoreVector(SDNode *N); 69 SDNode *SelectLoadParam(SDNode *N); 70 SDNode *SelectStoreRetval(SDNode *N); 71 SDNode *SelectStoreParam(SDNode *N); 72 SDNode *SelectAddrSpaceCast(SDNode *N); 73 SDNode *SelectTextureIntrinsic(SDNode *N); 74 SDNode *SelectSurfaceIntrinsic(SDNode *N); 75 SDNode *SelectBFE(SDNode *N); 76 77 inline SDValue getI32Imm(unsigned Imm) { 78 return CurDAG->getTargetConstant(Imm, MVT::i32); 79 } 80 81 // Match direct address complex pattern. 82 bool SelectDirectAddr(SDValue N, SDValue &Address); 83 84 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base, 85 SDValue &Offset, MVT mvt); 86 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base, 87 SDValue &Offset); 88 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base, 89 SDValue &Offset); 90 91 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base, 92 SDValue &Offset, MVT mvt); 93 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base, 94 SDValue &Offset); 95 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base, 96 SDValue &Offset); 97 98 bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const; 99 100 }; 101 } 102
