/external/llvm/lib/CodeGen/ |
DFAPacketizer.cpp | 108 DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, 116 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, 118 ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) { 129 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, 133 VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
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CalcSpillWeights.cpp | 27 const MachineLoopInfo &MLI, 34 VirtRegAuxInfo VRAI(MF, LIS, MLI, MBFI, norm);
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MachineBlockFrequencyInfo.cpp | 143 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); 146 MBFI->doFunction(&F, &MBPI, &MLI);
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PHIElimination.cpp | 82 MachineLoopInfo *MLI); 140 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>(); 142 Changed |= SplitPHIEdges(MF, *I, MLI); 547 MachineLoopInfo *MLI) { 551 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr; 568 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
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UnreachableBlockElim.cpp | 125 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>(); 144 if (MLI) MLI->removeBlock(BB);
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PostRASchedulerList.cpp | 135 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, 191 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, 195 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) { 253 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); 287 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
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MachineBlockPlacement.cpp | 182 const MachineLoopInfo *MLI; 677 if (MachineLoop *ExitLoop = MLI->getLoopFor(*SI)) { [all...] |
MachineBasicBlock.cpp | 932 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>()) 933 if (MachineLoop *TIL = MLI->getLoopFor(this)) { 936 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) { [all...] |
MachineLICM.cpp | 75 MachineLoopInfo *MLI; // Current MachineLoopInfo 355 MLI = &getAnalysis<MachineLoopInfo>(); 359 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end()); 515 const MachineLoop *ML = MLI->getLoopFor(BB); 709 const MachineLoop *ML = MLI->getLoopFor(BB); [all...] |
ScheduleDAGInstrs.cpp | 53 const MachineLoopInfo &mli, 58 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis), [all...] |
MachineScheduler.cpp | 88 MF(nullptr), MLI(nullptr), MDT(nullptr), PassConfig(nullptr), AA(nullptr), LIS(nullptr) { 308 MLI = &getAnalysis<MachineLoopInfo>(); [all...] |
/external/llvm/include/llvm/CodeGen/ |
CalcSpillWeights.h | 71 const MachineLoopInfo &MLI,
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DFAPacketizer.h | 111 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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ScheduleDAGInstrs.h | 78 const MachineLoopInfo &MLI; 157 const MachineLoopInfo &mli,
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MachineScheduler.h | 104 const MachineLoopInfo *MLI; 253 : ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, IsPostRA,
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/external/llvm/lib/Target/R600/ |
AMDILCFGStructurizer.cpp | 168 MLI = &getAnalysis<MachineLoopInfo>(); 169 DEBUG(dbgs() << "LoopInfo:\n"; PrintLoopinfo(*MLI);); 183 MachineLoopInfo *MLI; 369 MachineLoop *LoopRep = MLI->getLoopFor(MBB); 388 MachineLoop *LoopRep = MLI->getLoopFor(MBB); 756 for (MachineLoopInfo::iterator It = MLI->begin(), 757 E = MLI->end(); It != E; ++It) { [all...] |
R600Packetizer.cpp | 151 R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, 153 : VLIWPacketizerList(MF, MLI, MDT, true), 332 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); 336 R600PacketizerList Packetizer(Fn, MLI, MDT);
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/external/llvm/lib/Target/Hexagon/ |
HexagonVLIWPacketizer.cpp | 120 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, 187 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT, 189 : VLIWPacketizerList(MF, MLI, MDT, true){ 195 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); 200 HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI); [all...] |
HexagonHardwareLoops.cpp | 64 MachineLoopInfo *MLI; 301 MLI = &getAnalysis<MachineLoopInfo>(); 308 for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end(); [all...] |
HexagonMachineScheduler.cpp | 148 << " at loop depth " << MLI.getLoopDepth(BB)
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