1 /* 2 * Copyright (c) 2011 Intel Corporation. All Rights Reserved. 3 * Copyright (c) Imagination Technologies Limited, UK 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 27 /*! 28 ****************************************************************************** 29 @file : /work/sim/msvdx/register_includes/msvdx_core_regs_io2.h 30 31 @brief 32 33 @Author <Autogenerated> 34 35 <b>Description:</b>\n 36 This file contains the MSVDX_CORE_REGS_IO2_H Defintions. 37 38 <b>Platform:</b>\n 39 ? 40 41 @Version 42 1.0 43 44 ******************************************************************************/ 45 46 #if !defined (__MSVDX_CORE_REGS_IO2_H__) 47 #define __MSVDX_CORE_REGS_IO2_H__ 48 49 #ifdef __cplusplus 50 extern "C" { 51 #endif 52 53 54 #define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_OFFSET (0x0094) 55 #define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_STRIDE (4) 56 #define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_NO_ENTRIES (4) 57 58 // MSVDX_CORE CR_MMU_DIR_LIST_BASE CR_MMU_DIR_LIST_BASE_ADDR 59 #define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_CR_MMU_DIR_LIST_BASE_ADDR_MASK (0xFFFFF000) 60 #define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_CR_MMU_DIR_LIST_BASE_ADDR_LSBMASK (0x000FFFFF) 61 #define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_CR_MMU_DIR_LIST_BASE_ADDR_SHIFT (12) 62 63 #define MSVDX_CORE_CR_MMU_TILE_OFFSET (0x00D4) 64 #define MSVDX_CORE_CR_MMU_TILE_STRIDE (4) 65 #define MSVDX_CORE_CR_MMU_TILE_NO_ENTRIES (4) 66 67 // MSVDX_CORE CR_MMU_TILE CR_TILE_MIN_ADDR 68 #define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MIN_ADDR_MASK (0x00000FFF) 69 #define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MIN_ADDR_LSBMASK (0x00000FFF) 70 #define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MIN_ADDR_SHIFT (0) 71 72 // MSVDX_CORE CR_MMU_TILE CR_TILE_MAX_ADDR 73 #define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MAX_ADDR_MASK (0x00FFF000) 74 #define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MAX_ADDR_LSBMASK (0x00000FFF) 75 #define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MAX_ADDR_SHIFT (12) 76 77 // MSVDX_CORE CR_MMU_TILE CR_TILE_CFG 78 #define MSVDX_CORE_CR_MMU_TILE_CR_TILE_CFG_MASK (0x0F000000) 79 #define MSVDX_CORE_CR_MMU_TILE_CR_TILE_CFG_LSBMASK (0x0000000F) 80 #define MSVDX_CORE_CR_MMU_TILE_CR_TILE_CFG_SHIFT (24) 81 82 #define MSVDX_CORE_CR_MSVDX_CONTROL_OFFSET (0x0000) 83 84 // MSVDX_CORE CR_MSVDX_CONTROL CR_ENDIAN 85 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_ENDIAN_MASK (0x00000001) 86 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_ENDIAN_LSBMASK (0x00000001) 87 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_ENDIAN_SHIFT (0) 88 89 // MSVDX_CORE CR_MSVDX_CONTROL CR_MSVDX_SOFT_RESET 90 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK (0x00000100) 91 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_LSBMASK (0x00000001) 92 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_SHIFT (8) 93 94 // MSVDX_CORE CR_MSVDX_CONTROL DMAC_CH0_SELECT 95 #define MSVDX_CORE_CR_MSVDX_CONTROL_DMAC_CH0_SELECT_MASK (0x00001000) 96 #define MSVDX_CORE_CR_MSVDX_CONTROL_DMAC_CH0_SELECT_LSBMASK (0x00000001) 97 #define MSVDX_CORE_CR_MSVDX_CONTROL_DMAC_CH0_SELECT_SHIFT (12) 98 99 // MSVDX_CORE CR_MSVDX_CONTROL CR_MSVDX_FE_SOFT_RESET 100 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_MASK (0x00010000) 101 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_LSBMASK (0x00000001) 102 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_SHIFT (16) 103 104 // MSVDX_CORE CR_MSVDX_CONTROL CR_MSVDX_BE_SOFT_RESET 105 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_MASK (0x00100000) 106 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_LSBMASK (0x00000001) 107 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_SHIFT (20) 108 109 // MSVDX_CORE CR_MSVDX_CONTROL CR_MSVDX_VDMC_VDEB_SOFT_RESET 110 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VDMC_VDEB_SOFT_RESET_MASK (0x00200000) 111 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VDMC_VDEB_SOFT_RESET_LSBMASK (0x00000001) 112 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VDMC_VDEB_SOFT_RESET_SHIFT (21) 113 114 // MSVDX_CORE CR_MSVDX_CONTROL CR_MSVDX_VEC_MEMIF_SOFT_RESET 115 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_MASK (0x01000000) 116 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_LSBMASK (0x00000001) 117 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_SHIFT (24) 118 119 // MSVDX_CORE CR_MSVDX_CONTROL CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET 120 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_MASK (0x10000000) 121 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_LSBMASK (0x00000001) 122 #define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_SHIFT (28) 123 124 #define MSVDX_CORE_CR_MSVDX_INTERNAL_OFFSET (0x0004) 125 126 // MSVDX_CORE CR_MSVDX_INTERNAL CR_MPEG4_DP_SUPPORTED 127 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_DP_SUPPORTED_MASK (0x40000000) 128 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_DP_SUPPORTED_LSBMASK (0x00000001) 129 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_DP_SUPPORTED_SHIFT (30) 130 131 // MSVDX_CORE CR_MSVDX_INTERNAL CR_JPEG_SUPPORTED 132 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_JPEG_SUPPORTED_MASK (0x20000000) 133 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_JPEG_SUPPORTED_LSBMASK (0x00000001) 134 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_JPEG_SUPPORTED_SHIFT (29) 135 136 // MSVDX_CORE CR_MSVDX_INTERNAL CR_WMV_SUPPORTED 137 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_WMV_SUPPORTED_MASK (0x10000000) 138 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_WMV_SUPPORTED_LSBMASK (0x00000001) 139 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_WMV_SUPPORTED_SHIFT (28) 140 141 // MSVDX_CORE CR_MSVDX_INTERNAL CR_VC1_SUPPORTED 142 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_VC1_SUPPORTED_MASK (0x08000000) 143 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_VC1_SUPPORTED_LSBMASK (0x00000001) 144 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_VC1_SUPPORTED_SHIFT (27) 145 146 // MSVDX_CORE CR_MSVDX_INTERNAL CR_H264_SUPPORTED 147 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_H264_SUPPORTED_MASK (0x04000000) 148 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_H264_SUPPORTED_LSBMASK (0x00000001) 149 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_H264_SUPPORTED_SHIFT (26) 150 151 // MSVDX_CORE CR_MSVDX_INTERNAL CR_MPEG4_SUPPORTED 152 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_SUPPORTED_MASK (0x02000000) 153 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_SUPPORTED_LSBMASK (0x00000001) 154 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_SUPPORTED_SHIFT (25) 155 156 // MSVDX_CORE CR_MSVDX_INTERNAL CR_MPEG2_SUPPORTED 157 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG2_SUPPORTED_MASK (0x01000000) 158 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG2_SUPPORTED_LSBMASK (0x00000001) 159 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG2_SUPPORTED_SHIFT (24) 160 161 // MSVDX_CORE CR_MSVDX_INTERNAL CR_MSVDX_INTERNAL 162 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MSVDX_INTERNAL_MASK (0x00FFFFFF) 163 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MSVDX_INTERNAL_LSBMASK (0x00FFFFFF) 164 #define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MSVDX_INTERNAL_SHIFT (0) 165 166 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_OFFSET (0x0008) 167 168 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VEC_END_OF_SLICE 169 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_END_OF_SLICE_MASK (0x00000001) 170 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_END_OF_SLICE_LSBMASK (0x00000001) 171 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_END_OF_SLICE_SHIFT (0) 172 173 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VEC_ERROR_DETECTED_SR 174 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_SR_MASK (0x00000002) 175 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_SR_LSBMASK (0x00000001) 176 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_SR_SHIFT (1) 177 178 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VEC_ERROR_DETECTED_ENTDEC 179 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_ENTDEC_MASK (0x00000004) 180 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_ENTDEC_LSBMASK (0x00000001) 181 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_ENTDEC_SHIFT (2) 182 183 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VEC_RENDEC_ERROR 184 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_ERROR_MASK (0x00000008) 185 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_ERROR_LSBMASK (0x00000001) 186 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_ERROR_SHIFT (3) 187 188 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VEC_RENDEC_OVERFLOW 189 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_OVERFLOW_MASK (0x00000010) 190 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_OVERFLOW_LSBMASK (0x00000001) 191 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_OVERFLOW_SHIFT (4) 192 193 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VEC_RENDEC_UNDERFLOW 194 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_UNDERFLOW_MASK (0x00000020) 195 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_UNDERFLOW_LSBMASK (0x00000001) 196 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_UNDERFLOW_SHIFT (5) 197 198 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VEC_RENDEC_MTXBLOCK 199 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_MTXBLOCK_MASK (0x00000040) 200 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_MTXBLOCK_LSBMASK (0x00000001) 201 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_MTXBLOCK_SHIFT (6) 202 203 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VEC_RENDEC_END_OF_SLICE 204 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_END_OF_SLICE_MASK (0x00000080) 205 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_END_OF_SLICE_LSBMASK (0x00000001) 206 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_END_OF_SLICE_SHIFT (7) 207 208 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_MMU_FAULT_IRQ 209 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK (0x00000F00) 210 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_LSBMASK (0x0000000F) 211 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_SHIFT (8) 212 213 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_FE_WDT_CM0 214 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM0_MASK (0x00001000) 215 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM0_LSBMASK (0x00000001) 216 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM0_SHIFT (12) 217 218 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_FE_WDT_CM1 219 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM1_MASK (0x00002000) 220 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM1_LSBMASK (0x00000001) 221 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM1_SHIFT (13) 222 223 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_MTX_IRQ 224 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_MASK (0x00004000) 225 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_LSBMASK (0x00000001) 226 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_SHIFT (14) 227 228 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_MTX_GPIO_IRQ 229 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_GPIO_IRQ_MASK (0x00008000) 230 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_GPIO_IRQ_LSBMASK (0x00000001) 231 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_GPIO_IRQ_SHIFT (15) 232 233 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VDMC_IRQ 234 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDMC_IRQ_MASK (0x00010000) 235 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDMC_IRQ_LSBMASK (0x00000001) 236 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDMC_IRQ_SHIFT (16) 237 238 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VDEB_PICTURE_DONE_IRQ 239 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_PICTURE_DONE_IRQ_MASK (0x00020000) 240 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_PICTURE_DONE_IRQ_LSBMASK (0x00000001) 241 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_PICTURE_DONE_IRQ_SHIFT (17) 242 243 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VDEB_SLICE_DONE_IRQ 244 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_SLICE_DONE_IRQ_MASK (0x00040000) 245 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_SLICE_DONE_IRQ_LSBMASK (0x00000001) 246 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_SLICE_DONE_IRQ_SHIFT (18) 247 248 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VDEB_FLUSH_DONE_IRQ 249 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FLUSH_DONE_IRQ_MASK (0x00080000) 250 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FLUSH_DONE_IRQ_LSBMASK (0x00000001) 251 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FLUSH_DONE_IRQ_SHIFT (19) 252 253 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_DMAC_IRQ 254 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_DMAC_IRQ_MASK (0x00700000) 255 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_DMAC_IRQ_LSBMASK (0x00000007) 256 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_DMAC_IRQ_SHIFT (20) 257 258 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VDEB_FAULT_IRQ 259 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FAULT_IRQ_MASK (0x00800000) 260 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FAULT_IRQ_LSBMASK (0x00000001) 261 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FAULT_IRQ_SHIFT (23) 262 263 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_SYS_COMMAND_TIMEOUT_IRQ 264 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_COMMAND_TIMEOUT_IRQ_MASK (0x01000000) 265 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_COMMAND_TIMEOUT_IRQ_LSBMASK (0x00000001) 266 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_COMMAND_TIMEOUT_IRQ_SHIFT (24) 267 268 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_SYS_READ_TIMEOUT_IRQ 269 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_READ_TIMEOUT_IRQ_MASK (0x02000000) 270 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_READ_TIMEOUT_IRQ_LSBMASK (0x00000001) 271 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_READ_TIMEOUT_IRQ_SHIFT (25) 272 273 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_MTX_COMMAND_TIMEOUT_IRQ 274 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_COMMAND_TIMEOUT_IRQ_MASK (0x04000000) 275 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_COMMAND_TIMEOUT_IRQ_LSBMASK (0x00000001) 276 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_COMMAND_TIMEOUT_IRQ_SHIFT (26) 277 278 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_MTX_READ_TIMEOUT_IRQ 279 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_READ_TIMEOUT_IRQ_MASK (0x08000000) 280 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_READ_TIMEOUT_IRQ_LSBMASK (0x00000001) 281 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_READ_TIMEOUT_IRQ_SHIFT (27) 282 283 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_SYS_WDT 284 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_WDT_MASK (0x10000000) 285 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_WDT_LSBMASK (0x00000001) 286 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_WDT_SHIFT (28) 287 288 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_BE_WDT_CM0 289 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM0_MASK (0x20000000) 290 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM0_LSBMASK (0x00000001) 291 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM0_SHIFT (29) 292 293 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_BE_WDT_CM1 294 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM1_MASK (0x40000000) 295 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM1_LSBMASK (0x00000001) 296 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM1_SHIFT (30) 297 298 // MSVDX_CORE CR_MSVDX_INTERRUPT_STATUS CR_VEC_RENDEC_SLICE_SKIPPED 299 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_SLICE_SKIPPED_MASK (0x80000000) 300 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_SLICE_SKIPPED_LSBMASK (0x00000001) 301 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_SLICE_SKIPPED_SHIFT (31) 302 303 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_CLEAR_OFFSET (0x000C) 304 305 // MSVDX_CORE CR_MSVDX_INTERRUPT_CLEAR CR_IRQ_CLEAR 306 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_CLEAR_CR_IRQ_CLEAR_MASK (0xFFFFFFFF) 307 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_CLEAR_CR_IRQ_CLEAR_LSBMASK (0xFFFFFFFF) 308 #define MSVDX_CORE_CR_MSVDX_INTERRUPT_CLEAR_CR_IRQ_CLEAR_SHIFT (0) 309 310 #define MSVDX_CORE_CR_MSVDX_HOST_INTERRUPT_ENABLE_OFFSET (0x0010) 311 312 // MSVDX_CORE CR_MSVDX_HOST_INTERRUPT_ENABLE CR_HOST_IRQ_ENABLE 313 #define MSVDX_CORE_CR_MSVDX_HOST_INTERRUPT_ENABLE_CR_HOST_IRQ_ENABLE_MASK (0xFFFFFFFF) 314 #define MSVDX_CORE_CR_MSVDX_HOST_INTERRUPT_ENABLE_CR_HOST_IRQ_ENABLE_LSBMASK (0xFFFFFFFF) 315 #define MSVDX_CORE_CR_MSVDX_HOST_INTERRUPT_ENABLE_CR_HOST_IRQ_ENABLE_SHIFT (0) 316 317 #define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT1_ENABLE_OFFSET (0x0014) 318 319 // MSVDX_CORE CR_MSVDX_MTX_INTERRUPT1_ENABLE CR_MTX_IRQ1_ENABLE 320 #define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT1_ENABLE_CR_MTX_IRQ1_ENABLE_MASK (0xFFFFFFFF) 321 #define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT1_ENABLE_CR_MTX_IRQ1_ENABLE_LSBMASK (0xFFFFFFFF) 322 #define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT1_ENABLE_CR_MTX_IRQ1_ENABLE_SHIFT (0) 323 324 #define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT2_ENABLE_OFFSET (0x0018) 325 326 // MSVDX_CORE CR_MSVDX_MTX_INTERRUPT2_ENABLE CR_MTX_IRQ2_ENABLE 327 #define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT2_ENABLE_CR_MTX_IRQ2_ENABLE_MASK (0xFFFFFFFF) 328 #define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT2_ENABLE_CR_MTX_IRQ2_ENABLE_LSBMASK (0xFFFFFFFF) 329 #define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT2_ENABLE_CR_MTX_IRQ2_ENABLE_SHIFT (0) 330 331 #define MSVDX_CORE_CR_MSVDX_RSVD0_OFFSET (0x001C) 332 333 // MSVDX_CORE CR_MSVDX_RSVD0 CR_RSVD0 334 #define MSVDX_CORE_CR_MSVDX_RSVD0_CR_RSVD0_MASK (0xFFFFFFFF) 335 #define MSVDX_CORE_CR_MSVDX_RSVD0_CR_RSVD0_LSBMASK (0xFFFFFFFF) 336 #define MSVDX_CORE_CR_MSVDX_RSVD0_CR_RSVD0_SHIFT (0) 337 338 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_OFFSET (0x0020) 339 340 // MSVDX_CORE CR_MSVDX_MAN_CLK_ENABLE CR_CORE_MAN_CLK_ENABLE 341 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK (0x00000001) 342 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_LSBMASK (0x00000001) 343 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_SHIFT (0) 344 345 // MSVDX_CORE CR_MSVDX_MAN_CLK_ENABLE CR_VDEB_PROCESS_MAN_CLK_ENABLE 346 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_MASK (0x00000002) 347 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_LSBMASK (0x00000001) 348 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_SHIFT (1) 349 350 // MSVDX_CORE CR_MSVDX_MAN_CLK_ENABLE CR_VDEB_ACCESS_MAN_CLK_ENABLE 351 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_MASK (0x00000004) 352 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_LSBMASK (0x00000001) 353 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_SHIFT (2) 354 355 // MSVDX_CORE CR_MSVDX_MAN_CLK_ENABLE CR_VDMC_MAN_CLK_ENABLE 356 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_MASK (0x00000008) 357 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_LSBMASK (0x00000001) 358 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_SHIFT (3) 359 360 // MSVDX_CORE CR_MSVDX_MAN_CLK_ENABLE CR_VEC_ENTDEC_MAN_CLK_ENABLE 361 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_MASK (0x00000010) 362 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_LSBMASK (0x00000001) 363 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_SHIFT (4) 364 365 // MSVDX_CORE CR_MSVDX_MAN_CLK_ENABLE CR_VEC_ITRANS_MAN_CLK_ENABLE 366 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_MASK (0x00000020) 367 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_LSBMASK (0x00000001) 368 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_SHIFT (5) 369 370 // MSVDX_CORE CR_MSVDX_MAN_CLK_ENABLE CR_MTX_MAN_CLK_ENABLE 371 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK (0x00000040) 372 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_LSBMASK (0x00000001) 373 #define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_SHIFT (6) 374 375 #define MSVDX_CORE_CR_MSVDX_RTM_OFFSET (0x0024) 376 377 // MSVDX_CORE CR_MSVDX_RTM CR_RTM_B_BUS 378 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_B_BUS_MASK (0xFF000000) 379 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_B_BUS_LSBMASK (0x000000FF) 380 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_B_BUS_SHIFT (24) 381 382 // MSVDX_CORE CR_MSVDX_RTM CR_RTM_A_BUS 383 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_A_BUS_MASK (0x00FF0000) 384 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_A_BUS_LSBMASK (0x000000FF) 385 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_A_BUS_SHIFT (16) 386 387 // MSVDX_CORE CR_MSVDX_RTM CR_RTM_SELECT_B_MODULE 388 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_MODULE_MASK (0x00000300) 389 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_MODULE_LSBMASK (0x00000003) 390 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_MODULE_SHIFT (8) 391 392 // MSVDX_CORE CR_MSVDX_RTM CR_RTM_SELECT_A_MODULE 393 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_MODULE_MASK (0x000000C0) 394 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_MODULE_LSBMASK (0x00000003) 395 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_MODULE_SHIFT (6) 396 397 // MSVDX_CORE CR_MSVDX_RTM CR_RTM_SELECT_B 398 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_MASK (0x00000038) 399 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_LSBMASK (0x00000007) 400 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_SHIFT (3) 401 402 // MSVDX_CORE CR_MSVDX_RTM CR_RTM_SELECT_A 403 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_MASK (0x00000007) 404 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_LSBMASK (0x00000007) 405 #define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_SHIFT (0) 406 407 #define MSVDX_CORE_CR_MSVDX_COMMAND_SPACE_OFFSET (0x0028) 408 409 // MSVDX_CORE CR_MSVDX_COMMAND_SPACE CR_MSVDX_CMD_BUFFER_SPACE 410 #define MSVDX_CORE_CR_MSVDX_COMMAND_SPACE_CR_MSVDX_CMD_BUFFER_SPACE_MASK (0xFFFFFFFF) 411 #define MSVDX_CORE_CR_MSVDX_COMMAND_SPACE_CR_MSVDX_CMD_BUFFER_SPACE_LSBMASK (0xFFFFFFFF) 412 #define MSVDX_CORE_CR_MSVDX_COMMAND_SPACE_CR_MSVDX_CMD_BUFFER_SPACE_SHIFT (0) 413 414 #define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_OFFSET (0x002C) 415 416 // MSVDX_CORE CR_MSVDX_RENDEC_SPACE CR_MSVDX_RENDEC_WRITE_SPACE 417 #define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_WRITE_SPACE_MASK (0x00000001) 418 #define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_WRITE_SPACE_LSBMASK (0x00000001) 419 #define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_WRITE_SPACE_SHIFT (0) 420 421 // MSVDX_CORE CR_MSVDX_RENDEC_SPACE CR_MSVDX_RENDEC_READ_AVAILABLE 422 #define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_READ_AVAILABLE_MASK (0x00000010) 423 #define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_READ_AVAILABLE_LSBMASK (0x00000001) 424 #define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_READ_AVAILABLE_SHIFT (4) 425 426 #define MSVDX_CORE_CR_MSVDX_CORE_ID_OFFSET (0x0030) 427 428 // MSVDX_CORE CR_MSVDX_CORE_ID CR_CR_MSVDX_CORE_CONFIG 429 #define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CR_MSVDX_CORE_CONFIG_MASK (0x0000FFFF) 430 #define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CR_MSVDX_CORE_CONFIG_LSBMASK (0x0000FFFF) 431 #define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CR_MSVDX_CORE_CONFIG_SHIFT (0) 432 433 // MSVDX_CORE CR_MSVDX_CORE_ID CR_CORE_ID 434 #define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CORE_ID_MASK (0x00FF0000) 435 #define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CORE_ID_LSBMASK (0x000000FF) 436 #define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CORE_ID_SHIFT (16) 437 438 // MSVDX_CORE CR_MSVDX_CORE_ID CR_GROUP_ID 439 #define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_GROUP_ID_MASK (0xFF000000) 440 #define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_GROUP_ID_LSBMASK (0x000000FF) 441 #define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_GROUP_ID_SHIFT (24) 442 443 #define MSVDX_CORE_CR_MSVDX_CORE_REV_OFFSET (0x0040) 444 445 // MSVDX_CORE CR_MSVDX_CORE_REV CR_MSVDX_MAINT_REV 446 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAINT_REV_MASK (0x000000FF) 447 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAINT_REV_LSBMASK (0x000000FF) 448 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAINT_REV_SHIFT (0) 449 450 // MSVDX_CORE CR_MSVDX_CORE_REV CR_MSVDX_MINOR_REV 451 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MINOR_REV_MASK (0x0000FF00) 452 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MINOR_REV_LSBMASK (0x000000FF) 453 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MINOR_REV_SHIFT (8) 454 455 // MSVDX_CORE CR_MSVDX_CORE_REV CR_MSVDX_MAJOR_REV 456 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAJOR_REV_MASK (0x00FF0000) 457 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAJOR_REV_LSBMASK (0x000000FF) 458 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAJOR_REV_SHIFT (16) 459 460 // MSVDX_CORE CR_MSVDX_CORE_REV CR_MSVDX_DESIGNER 461 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_DESIGNER_MASK (0xFF000000) 462 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_DESIGNER_LSBMASK (0x000000FF) 463 #define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_DESIGNER_SHIFT (24) 464 465 #define MSVDX_CORE_CR_MSVDX_CORE_DES1_OFFSET (0x0050) 466 467 // MSVDX_CORE CR_MSVDX_CORE_DES1 CR_MSVDX_DESIGNER1 468 #define MSVDX_CORE_CR_MSVDX_CORE_DES1_CR_MSVDX_DESIGNER1_MASK (0xFFFFFFFF) 469 #define MSVDX_CORE_CR_MSVDX_CORE_DES1_CR_MSVDX_DESIGNER1_LSBMASK (0xFFFFFFFF) 470 #define MSVDX_CORE_CR_MSVDX_CORE_DES1_CR_MSVDX_DESIGNER1_SHIFT (0) 471 472 #define MSVDX_CORE_CR_MSVDX_CORE_DES2_OFFSET (0x0060) 473 474 // MSVDX_CORE CR_MSVDX_CORE_DES2 CR_MSVDX_DESIGNER2 475 #define MSVDX_CORE_CR_MSVDX_CORE_DES2_CR_MSVDX_DESIGNER2_MASK (0xFFFFFFFF) 476 #define MSVDX_CORE_CR_MSVDX_CORE_DES2_CR_MSVDX_DESIGNER2_LSBMASK (0xFFFFFFFF) 477 #define MSVDX_CORE_CR_MSVDX_CORE_DES2_CR_MSVDX_DESIGNER2_SHIFT (0) 478 479 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_OFFSET (0x0064) 480 481 // MSVDX_CORE CR_FE_MSVDX_WDT_CONTROL FE_WDT_ENABLE 482 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ENABLE_MASK (0x00010000) 483 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ENABLE_LSBMASK (0x00000001) 484 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ENABLE_SHIFT (16) 485 486 // MSVDX_CORE CR_FE_MSVDX_WDT_CONTROL FE_WDT_ACTION1 487 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION1_MASK (0x00003000) 488 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION1_LSBMASK (0x00000003) 489 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION1_SHIFT (12) 490 491 // MSVDX_CORE CR_FE_MSVDX_WDT_CONTROL FE_WDT_ACTION0 492 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION0_MASK (0x00000100) 493 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION0_LSBMASK (0x00000001) 494 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION0_SHIFT (8) 495 496 // MSVDX_CORE CR_FE_MSVDX_WDT_CONTROL FE_WDT_CLEAR_SELECT 497 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLEAR_SELECT_MASK (0x00000030) 498 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLEAR_SELECT_LSBMASK (0x00000003) 499 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLEAR_SELECT_SHIFT (4) 500 501 // MSVDX_CORE CR_FE_MSVDX_WDT_CONTROL FE_WDT_CLKDIV_SELECT 502 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLKDIV_SELECT_MASK (0x00000007) 503 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLKDIV_SELECT_LSBMASK (0x00000007) 504 #define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLKDIV_SELECT_SHIFT (0) 505 506 #define MSVDX_CORE_CR_FE_MSVDX_WDTIMER_OFFSET (0x0068) 507 508 // MSVDX_CORE CR_FE_MSVDX_WDTIMER FE_WDT_COUNTER 509 #define MSVDX_CORE_CR_FE_MSVDX_WDTIMER_FE_WDT_COUNTER_MASK (0x0000FFFF) 510 #define MSVDX_CORE_CR_FE_MSVDX_WDTIMER_FE_WDT_COUNTER_LSBMASK (0x0000FFFF) 511 #define MSVDX_CORE_CR_FE_MSVDX_WDTIMER_FE_WDT_COUNTER_SHIFT (0) 512 513 #define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_OFFSET (0x006C) 514 515 // MSVDX_CORE CR_FE_MSVDX_WDT_COMPAREMATCH FE_WDT_CM1 516 #define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM1_MASK (0xFFFF0000) 517 #define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM1_LSBMASK (0x0000FFFF) 518 #define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM1_SHIFT (16) 519 520 // MSVDX_CORE CR_FE_MSVDX_WDT_COMPAREMATCH FE_WDT_CM0 521 #define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM0_MASK (0x0000FFFF) 522 #define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM0_LSBMASK (0x0000FFFF) 523 #define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM0_SHIFT (0) 524 525 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_OFFSET (0x0070) 526 527 // MSVDX_CORE CR_BE_MSVDX_WDT_CONTROL BE_WDT_ENABLE 528 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ENABLE_MASK (0x00010000) 529 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ENABLE_LSBMASK (0x00000001) 530 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ENABLE_SHIFT (16) 531 532 // MSVDX_CORE CR_BE_MSVDX_WDT_CONTROL BE_WDT_ACTION1 533 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION1_MASK (0x00003000) 534 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION1_LSBMASK (0x00000003) 535 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION1_SHIFT (12) 536 537 // MSVDX_CORE CR_BE_MSVDX_WDT_CONTROL BE_WDT_ACTION0 538 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION0_MASK (0x00000100) 539 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION0_LSBMASK (0x00000001) 540 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION0_SHIFT (8) 541 542 // MSVDX_CORE CR_BE_MSVDX_WDT_CONTROL BE_WDT_CLEAR_SELECT 543 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLEAR_SELECT_MASK (0x000000F0) 544 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLEAR_SELECT_LSBMASK (0x0000000F) 545 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLEAR_SELECT_SHIFT (4) 546 547 // MSVDX_CORE CR_BE_MSVDX_WDT_CONTROL BE_WDT_CLKDIV_SELECT 548 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLKDIV_SELECT_MASK (0x00000007) 549 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLKDIV_SELECT_LSBMASK (0x00000007) 550 #define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLKDIV_SELECT_SHIFT (0) 551 552 #define MSVDX_CORE_CR_BE_MSVDX_WDTIMER_OFFSET (0x0074) 553 554 // MSVDX_CORE CR_BE_MSVDX_WDTIMER BE_WDT_COUNTER 555 #define MSVDX_CORE_CR_BE_MSVDX_WDTIMER_BE_WDT_COUNTER_MASK (0x0000FFFF) 556 #define MSVDX_CORE_CR_BE_MSVDX_WDTIMER_BE_WDT_COUNTER_LSBMASK (0x0000FFFF) 557 #define MSVDX_CORE_CR_BE_MSVDX_WDTIMER_BE_WDT_COUNTER_SHIFT (0) 558 559 #define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_OFFSET (0x0078) 560 561 // MSVDX_CORE CR_BE_MSVDX_WDT_COMPAREMATCH BE_WDT_CM1 562 #define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM1_MASK (0xFFFF0000) 563 #define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM1_LSBMASK (0x0000FFFF) 564 #define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM1_SHIFT (16) 565 566 // MSVDX_CORE CR_BE_MSVDX_WDT_COMPAREMATCH BE_WDT_CM0 567 #define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM0_MASK (0x0000FFFF) 568 #define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM0_LSBMASK (0x0000FFFF) 569 #define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM0_SHIFT (0) 570 571 #define MSVDX_CORE_CR_MMU_CONTROL0_OFFSET (0x0080) 572 573 // MSVDX_CORE CR_MMU_CONTROL0 CR_MMU_INVALDC 574 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_INVALDC_MASK (0x00000008) 575 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_INVALDC_LSBMASK (0x00000001) 576 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_INVALDC_SHIFT (3) 577 578 // MSVDX_CORE CR_MMU_CONTROL0 CR_MMU_FLUSH 579 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_FLUSH_MASK (0x00000004) 580 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_FLUSH_LSBMASK (0x00000001) 581 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_FLUSH_SHIFT (2) 582 583 // MSVDX_CORE CR_MMU_CONTROL0 CR_MMU_PAUSE 584 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_PAUSE_MASK (0x00000002) 585 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_PAUSE_LSBMASK (0x00000001) 586 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_PAUSE_SHIFT (1) 587 588 // MSVDX_CORE CR_MMU_CONTROL0 CR_MMU_NOREORDER 589 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_NOREORDER_MASK (0x00000001) 590 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_NOREORDER_LSBMASK (0x00000001) 591 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_NOREORDER_SHIFT (0) 592 593 // MSVDX_CORE CR_MMU_CONTROL0 CR_FLOWRATE_DMAC 594 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_DMAC_MASK (0x00000700) 595 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_DMAC_LSBMASK (0x00000007) 596 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_DMAC_SHIFT (8) 597 598 // MSVDX_CORE CR_MMU_CONTROL0 CR_FLOWRATE_VEC 599 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VEC_MASK (0x00003800) 600 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VEC_LSBMASK (0x00000007) 601 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VEC_SHIFT (11) 602 603 // MSVDX_CORE CR_MMU_CONTROL0 CR_FLOWRATE_VDMC 604 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDMC_MASK (0x0001C000) 605 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDMC_LSBMASK (0x00000007) 606 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDMC_SHIFT (14) 607 608 // MSVDX_CORE CR_MMU_CONTROL0 CR_FLOWRATE_VDEB 609 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDEB_MASK (0x000E0000) 610 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDEB_LSBMASK (0x00000007) 611 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDEB_SHIFT (17) 612 613 // MSVDX_CORE CR_MMU_CONTROL0 CR_MMU_BYPASS_DMAC 614 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_DMAC_MASK (0x01000000) 615 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_DMAC_LSBMASK (0x00000001) 616 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_DMAC_SHIFT (24) 617 618 // MSVDX_CORE CR_MMU_CONTROL0 CR_MMU_BYPASS_VEC 619 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VEC_MASK (0x02000000) 620 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VEC_LSBMASK (0x00000001) 621 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VEC_SHIFT (25) 622 623 // MSVDX_CORE CR_MMU_CONTROL0 CR_MMU_BYPASS_VDMC 624 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDMC_MASK (0x04000000) 625 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDMC_LSBMASK (0x00000001) 626 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDMC_SHIFT (26) 627 628 // MSVDX_CORE CR_MMU_CONTROL0 CR_MMU_BYPASS_VDEB 629 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDEB_MASK (0x08000000) 630 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDEB_LSBMASK (0x00000001) 631 #define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDEB_SHIFT (27) 632 633 #define MSVDX_CORE_CR_MMU_CONTROL1_OFFSET (0x0084) 634 635 // MSVDX_CORE CR_MMU_CONTROL1 CR_MMU_TTE_THRESHOLD 636 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_TTE_THRESHOLD_MASK (0x00000FFF) 637 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_TTE_THRESHOLD_LSBMASK (0x00000FFF) 638 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_TTE_THRESHOLD_SHIFT (0) 639 640 // MSVDX_CORE CR_MMU_CONTROL1 CR_MMU_ADT_TTE 641 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_ADT_TTE_MASK (0x000FF000) 642 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_ADT_TTE_LSBMASK (0x000000FF) 643 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_ADT_TTE_SHIFT (12) 644 645 // MSVDX_CORE CR_MMU_CONTROL1 CR_MMU_BEST_COUNT 646 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_BEST_COUNT_MASK (0x0FF00000) 647 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_BEST_COUNT_LSBMASK (0x000000FF) 648 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_BEST_COUNT_SHIFT (20) 649 650 // MSVDX_CORE CR_MMU_CONTROL1 CR_MMU_PAGE_SIZE 651 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_PAGE_SIZE_MASK (0xF0000000) 652 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_PAGE_SIZE_LSBMASK (0x0000000F) 653 #define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_PAGE_SIZE_SHIFT (28) 654 655 #define MSVDX_CORE_CR_MMU_BANK_INDEX_OFFSET (0x0088) 656 657 // MSVDX_CORE CR_MMU_BANK_INDEX CR_MMU_BANK_SELECT 658 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_MASK (0x00000002) 659 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_LSBMASK (0x00000001) 660 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_SHIFT (1) 661 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_NO_REPS (2) 662 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_SIZE (1) 663 664 // MSVDX_CORE CR_MMU_BANK_INDEX CR_MMU_BANK_N_INDEX_M 665 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_MASK (0x0000C000) 666 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_LSBMASK (0x00000003) 667 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_SHIFT (14) 668 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_NO_REPS (4) 669 #define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_SIZE (2) 670 671 #define MSVDX_CORE_CR_MMU_STATUS_OFFSET (0x008C) 672 673 // MSVDX_CORE CR_MMU_STATUS CR_MMU_FAULT_ADDR 674 #define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_FAULT_ADDR_MASK (0xFFFFF000) 675 #define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_FAULT_ADDR_LSBMASK (0x000FFFFF) 676 #define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_FAULT_ADDR_SHIFT (12) 677 678 // MSVDX_CORE CR_MMU_STATUS CR_MMU_PF_N_RW 679 #define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_PF_N_RW_MASK (0x00000001) 680 #define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_PF_N_RW_LSBMASK (0x00000001) 681 #define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_PF_N_RW_SHIFT (0) 682 683 #define MSVDX_CORE_CR_MMU_MEM_REQ_OFFSET (0x00D0) 684 685 // MSVDX_CORE CR_MMU_MEM_REQ CR_MEM_REQ_STAT_READS 686 #define MSVDX_CORE_CR_MMU_MEM_REQ_CR_MEM_REQ_STAT_READS_MASK (0x000000FF) 687 #define MSVDX_CORE_CR_MMU_MEM_REQ_CR_MEM_REQ_STAT_READS_LSBMASK (0x000000FF) 688 #define MSVDX_CORE_CR_MMU_MEM_REQ_CR_MEM_REQ_STAT_READS_SHIFT (0) 689 690 #define MSVDX_CORE_CR_MTX_DEBUG_OFFSET (0x00F0) 691 692 // MSVDX_CORE CR_MTX_DEBUG CR_MTX_LAST_RAM_BANK_SIZE 693 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_LAST_RAM_BANK_SIZE_MASK (0x0F000000) 694 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_LAST_RAM_BANK_SIZE_LSBMASK (0x0000000F) 695 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_LAST_RAM_BANK_SIZE_SHIFT (24) 696 697 // MSVDX_CORE CR_MTX_DEBUG CR_MTX_RAM_BANK_SIZE 698 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANK_SIZE_MASK (0x000F0000) 699 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANK_SIZE_LSBMASK (0x0000000F) 700 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANK_SIZE_SHIFT (16) 701 702 // MSVDX_CORE CR_MTX_DEBUG CR_MTX_RAM_BANKS 703 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANKS_MASK (0x00000F00) 704 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANKS_LSBMASK (0x0000000F) 705 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANKS_SHIFT (8) 706 707 // MSVDX_CORE CR_MTX_DEBUG CR_MTX_DBG_GPIO_OUT 708 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_OUT_MASK (0x00000018) 709 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_OUT_LSBMASK (0x00000003) 710 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_OUT_SHIFT (3) 711 712 // MSVDX_CORE CR_MTX_DEBUG CR_MTX_DBG_IS_SLAVE 713 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_IS_SLAVE_MASK (0x00000004) 714 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_IS_SLAVE_LSBMASK (0x00000001) 715 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_IS_SLAVE_SHIFT (2) 716 717 // MSVDX_CORE CR_MTX_DEBUG CR_MTX_DBG_GPIO_IN 718 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_IN_MASK (0x00000003) 719 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_IN_LSBMASK (0x00000003) 720 #define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_IN_SHIFT (0) 721 722 #define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_OFFSET (0x00F4) 723 724 // MSVDX_CORE CR_SYS_MSVDX_WDT_CONTROL SYS_WDT_ENABLE 725 #define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_ENABLE_MASK (0x00010000) 726 #define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_ENABLE_LSBMASK (0x00000001) 727 #define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_ENABLE_SHIFT (16) 728 729 // MSVDX_CORE CR_SYS_MSVDX_WDT_CONTROL SYS_WDT_CLKDIV_SELECT 730 #define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_CLKDIV_SELECT_MASK (0x00000007) 731 #define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_CLKDIV_SELECT_LSBMASK (0x00000007) 732 #define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_CLKDIV_SELECT_SHIFT (0) 733 734 #define MSVDX_CORE_CR_SYS_MSVDX_WDTIMER_OFFSET (0x00F8) 735 736 // MSVDX_CORE CR_SYS_MSVDX_WDTIMER SYS_WDT_COUNTER 737 #define MSVDX_CORE_CR_SYS_MSVDX_WDTIMER_SYS_WDT_COUNTER_MASK (0x0000FFFF) 738 #define MSVDX_CORE_CR_SYS_MSVDX_WDTIMER_SYS_WDT_COUNTER_LSBMASK (0x0000FFFF) 739 #define MSVDX_CORE_CR_SYS_MSVDX_WDTIMER_SYS_WDT_COUNTER_SHIFT (0) 740 741 742 743 #ifdef __cplusplus 744 } 745 #endif 746 747 #endif /* __MSVDX_CORE_REGS_IO2_H__ */ 748
