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      1 /* Copyright (C) 2007-2008 The Android Open Source Project
      2 **
      3 ** This software is licensed under the terms of the GNU General Public
      4 ** License version 2, as published by the Free Software Foundation, and
      5 ** may be copied, distributed, and modified under those terms.
      6 **
      7 ** This program is distributed in the hope that it will be useful,
      8 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
      9 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     10 ** GNU General Public License for more details.
     11 */
     12 #include "cpu.h"
     13 #include "migration/qemu-file.h"
     14 #include "hw/arm/pic.h"
     15 #include "hw/android/goldfish/device.h"
     16 #include "hw/android/goldfish/vmem.h"
     17 #include "android/utils/debug.h"
     18 
     19 #define PDEV_BUS_OP_DONE        (0x00)
     20 #define PDEV_BUS_OP_REMOVE_DEV  (0x04)
     21 #define PDEV_BUS_OP_ADD_DEV     (0x08)
     22 
     23 #define PDEV_BUS_OP_INIT        (0x00)
     24 
     25 #define PDEV_BUS_OP             (0x00)
     26 #define PDEV_BUS_GET_NAME       (0x04)
     27 #define PDEV_BUS_NAME_LEN       (0x08)
     28 #define PDEV_BUS_ID             (0x0c)
     29 #define PDEV_BUS_IO_BASE        (0x10)
     30 #define PDEV_BUS_IO_SIZE        (0x14)
     31 #define PDEV_BUS_IRQ            (0x18)
     32 #define PDEV_BUS_IRQ_COUNT      (0x1c)
     33 
     34 #define PDEV_BUS_NAME_ADDR_HIGH  (0x20)
     35 
     36 struct bus_state {
     37     struct goldfish_device dev;
     38     struct goldfish_device *current;
     39     uint64_t name_addr_high;
     40 };
     41 
     42 qemu_irq *goldfish_pic;
     43 static struct goldfish_device *first_device;
     44 static struct goldfish_device *last_device;
     45 uint32_t goldfish_free_base;
     46 uint32_t goldfish_free_irq;
     47 
     48 int goldfish_64bit_guest = 0;
     49 
     50 int goldfish_guest_is_64bit()
     51 {
     52     return goldfish_64bit_guest;
     53 }
     54 
     55 void goldfish_device_set_irq(struct goldfish_device *dev, int irq, int level)
     56 {
     57     if(irq >= dev->irq_count)
     58         cpu_abort (cpu_single_env, "goldfish_device_set_irq: Bad irq %d >= %d\n", irq, dev->irq_count);
     59     else
     60         qemu_set_irq(goldfish_pic[dev->irq + irq], level);
     61 }
     62 
     63 int goldfish_add_device_no_io(struct goldfish_device *dev)
     64 {
     65     if(dev->base == 0) {
     66         dev->base = goldfish_free_base;
     67         goldfish_free_base += dev->size;
     68     }
     69     if(dev->irq == 0 && dev->irq_count > 0) {
     70         dev->irq = goldfish_free_irq;
     71         goldfish_free_irq += dev->irq_count;
     72 #ifdef TARGET_I386
     73         /* Make sure that we pass by the reserved IRQs. */
     74         while (goldfish_free_irq == GFD_KBD_IRQ ||
     75                goldfish_free_irq == GFD_RTC_IRQ ||
     76                goldfish_free_irq == GFD_MOUSE_IRQ ||
     77                goldfish_free_irq == GFD_ERR_IRQ) {
     78             goldfish_free_irq++;
     79         }
     80 #endif
     81         if (goldfish_free_irq >= GFD_MAX_IRQ) {
     82             derror("Goldfish device has exceeded available IRQ number.");
     83             exit(1);
     84         }
     85     }
     86     //printf("goldfish_add_device: %s, base %x %x, irq %d %d\n",
     87     //       dev->name, dev->base, dev->size, dev->irq, dev->irq_count);
     88     dev->next = NULL;
     89     if(last_device) {
     90         last_device->next = dev;
     91     }
     92     else {
     93         first_device = dev;
     94     }
     95     last_device = dev;
     96     return 0;
     97 }
     98 
     99 int goldfish_device_add(struct goldfish_device *dev,
    100                        CPUReadMemoryFunc **mem_read,
    101                        CPUWriteMemoryFunc **mem_write,
    102                        void *opaque)
    103 {
    104     int iomemtype;
    105     goldfish_add_device_no_io(dev);
    106     iomemtype = cpu_register_io_memory(mem_read, mem_write, opaque);
    107     cpu_register_physical_memory(dev->base, dev->size, iomemtype);
    108     return 0;
    109 }
    110 
    111 static uint32_t goldfish_bus_read(void *opaque, hwaddr offset)
    112 {
    113     struct bus_state *s = (struct bus_state *)opaque;
    114 
    115     switch (offset) {
    116         case PDEV_BUS_OP:
    117             if(s->current) {
    118                 s->current->reported_state = 1;
    119                 s->current = s->current->next;
    120             }
    121             else {
    122                 s->current = first_device;
    123             }
    124             while(s->current && s->current->reported_state == 1)
    125                 s->current = s->current->next;
    126             if(s->current)
    127                 return PDEV_BUS_OP_ADD_DEV;
    128             else {
    129                 goldfish_device_set_irq(&s->dev, 0, 0);
    130                 return PDEV_BUS_OP_DONE;
    131             }
    132 
    133         case PDEV_BUS_NAME_LEN:
    134             return s->current ? strlen(s->current->name) : 0;
    135         case PDEV_BUS_ID:
    136             return s->current ? s->current->id : 0;
    137         case PDEV_BUS_IO_BASE:
    138             return s->current ? s->current->base : 0;
    139         case PDEV_BUS_IO_SIZE:
    140             return s->current ? s->current->size : 0;
    141         case PDEV_BUS_IRQ:
    142             return s->current ? s->current->irq : 0;
    143         case PDEV_BUS_IRQ_COUNT:
    144             return s->current ? s->current->irq_count : 0;
    145     default:
    146         cpu_abort (cpu_single_env, "goldfish_bus_read: Bad offset %x\n", offset);
    147         return 0;
    148     }
    149 }
    150 
    151 static void goldfish_bus_op_init(struct bus_state *s)
    152 {
    153     struct goldfish_device *dev = first_device;
    154     while(dev) {
    155         dev->reported_state = 0;
    156         dev = dev->next;
    157     }
    158     s->current = NULL;
    159     goldfish_device_set_irq(&s->dev, 0, first_device != NULL);
    160 }
    161 
    162 static void goldfish_bus_write(void *opaque, hwaddr offset, uint32_t value)
    163 {
    164     struct bus_state *s = (struct bus_state *)opaque;
    165 
    166     switch(offset) {
    167         case PDEV_BUS_OP:
    168             switch(value) {
    169                 case PDEV_BUS_OP_INIT:
    170                     goldfish_bus_op_init(s);
    171                     break;
    172                 default:
    173                     cpu_abort (cpu_single_env, "goldfish_bus_write: Bad PDEV_BUS_OP value %x\n", value);
    174             };
    175             break;
    176         case PDEV_BUS_GET_NAME:
    177             if(s->current) {
    178                 target_ulong name = (target_ulong)(s->name_addr_high | value);
    179                 safe_memory_rw_debug(current_cpu, name, (void*)s->current->name, strlen(s->current->name), 1);
    180             }
    181             break;
    182         case PDEV_BUS_NAME_ADDR_HIGH:
    183             s->name_addr_high = ((uint64_t)value << 32);
    184             goldfish_64bit_guest = 1;
    185             break;
    186         default:
    187             cpu_abort (cpu_single_env, "goldfish_bus_write: Bad offset %x\n", offset);
    188     }
    189 }
    190 
    191 static CPUReadMemoryFunc *goldfish_bus_readfn[] = {
    192     goldfish_bus_read,
    193     goldfish_bus_read,
    194     goldfish_bus_read
    195 };
    196 
    197 static CPUWriteMemoryFunc *goldfish_bus_writefn[] = {
    198     goldfish_bus_write,
    199     goldfish_bus_write,
    200     goldfish_bus_write
    201 };
    202 
    203 
    204 static struct bus_state bus_state = {
    205     .dev = {
    206         .name = "goldfish_device_bus",
    207         .id = -1,
    208         .base = 0x10001000,
    209         .size = 0x1000,
    210         .irq = 1,
    211         .irq_count = 1,
    212     }
    213 };
    214 
    215 void goldfish_device_init(qemu_irq *pic, uint32_t base, uint32_t size, uint32_t irq, uint32_t irq_count)
    216 {
    217     goldfish_pic = pic;
    218     goldfish_free_base = base;
    219     goldfish_free_irq = irq;
    220 }
    221 
    222 int goldfish_device_bus_init(uint32_t base, uint32_t irq)
    223 {
    224     bus_state.dev.base = base;
    225     bus_state.dev.irq = irq;
    226 
    227     return goldfish_device_add(&bus_state.dev, goldfish_bus_readfn, goldfish_bus_writefn, &bus_state);
    228 }
    229 
    230