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      1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // Top-level implementation for the PowerPC target.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "PPCTargetMachine.h"
     15 #include "PPC.h"
     16 #include "llvm/CodeGen/Passes.h"
     17 #include "llvm/MC/MCStreamer.h"
     18 #include "llvm/PassManager.h"
     19 #include "llvm/Support/CommandLine.h"
     20 #include "llvm/Support/FormattedStream.h"
     21 #include "llvm/Support/TargetRegistry.h"
     22 #include "llvm/Target/TargetOptions.h"
     23 using namespace llvm;
     24 
     25 static cl::
     26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
     27                         cl::desc("Disable CTR loops for PPC"));
     28 
     29 static cl::opt<bool>
     30 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
     31   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
     32 
     33 extern "C" void LLVMInitializePowerPCTarget() {
     34   // Register the targets
     35   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
     36   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
     37   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
     38 }
     39 
     40 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
     41                                    StringRef FS, const TargetOptions &Options,
     42                                    Reloc::Model RM, CodeModel::Model CM,
     43                                    CodeGenOpt::Level OL, bool is64Bit)
     44     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
     45       Subtarget(TT, CPU, FS, *this, is64Bit, OL) {
     46   initAsmInfo();
     47 }
     48 
     49 void PPC32TargetMachine::anchor() { }
     50 
     51 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
     52                                        StringRef CPU, StringRef FS,
     53                                        const TargetOptions &Options,
     54                                        Reloc::Model RM, CodeModel::Model CM,
     55                                        CodeGenOpt::Level OL)
     56   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
     57 }
     58 
     59 void PPC64TargetMachine::anchor() { }
     60 
     61 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
     62                                        StringRef CPU,  StringRef FS,
     63                                        const TargetOptions &Options,
     64                                        Reloc::Model RM, CodeModel::Model CM,
     65                                        CodeGenOpt::Level OL)
     66   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
     67 }
     68 
     69 
     70 //===----------------------------------------------------------------------===//
     71 // Pass Pipeline Configuration
     72 //===----------------------------------------------------------------------===//
     73 
     74 namespace {
     75 /// PPC Code Generator Pass Configuration Options.
     76 class PPCPassConfig : public TargetPassConfig {
     77 public:
     78   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
     79     : TargetPassConfig(TM, PM) {}
     80 
     81   PPCTargetMachine &getPPCTargetMachine() const {
     82     return getTM<PPCTargetMachine>();
     83   }
     84 
     85   const PPCSubtarget &getPPCSubtarget() const {
     86     return *getPPCTargetMachine().getSubtargetImpl();
     87   }
     88 
     89   bool addPreISel() override;
     90   bool addILPOpts() override;
     91   bool addInstSelector() override;
     92   bool addPreRegAlloc() override;
     93   bool addPreSched2() override;
     94   bool addPreEmitPass() override;
     95 };
     96 } // namespace
     97 
     98 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
     99   return new PPCPassConfig(this, PM);
    100 }
    101 
    102 bool PPCPassConfig::addPreISel() {
    103   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
    104     addPass(createPPCCTRLoops(getPPCTargetMachine()));
    105 
    106   return false;
    107 }
    108 
    109 bool PPCPassConfig::addILPOpts() {
    110   addPass(&EarlyIfConverterID);
    111   return true;
    112 }
    113 
    114 bool PPCPassConfig::addInstSelector() {
    115   // Install an instruction selector.
    116   addPass(createPPCISelDag(getPPCTargetMachine()));
    117 
    118 #ifndef NDEBUG
    119   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
    120     addPass(createPPCCTRLoopsVerify());
    121 #endif
    122 
    123   addPass(createPPCVSXCopyPass());
    124   return false;
    125 }
    126 
    127 bool PPCPassConfig::addPreRegAlloc() {
    128   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
    129   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
    130              &PPCVSXFMAMutateID);
    131   return false;
    132 }
    133 
    134 bool PPCPassConfig::addPreSched2() {
    135   addPass(createPPCVSXCopyCleanupPass());
    136 
    137   if (getOptLevel() != CodeGenOpt::None)
    138     addPass(&IfConverterID);
    139 
    140   return true;
    141 }
    142 
    143 bool PPCPassConfig::addPreEmitPass() {
    144   if (getOptLevel() != CodeGenOpt::None)
    145     addPass(createPPCEarlyReturnPass());
    146   // Must run branch selection immediately preceding the asm printer.
    147   addPass(createPPCBranchSelectionPass());
    148   return false;
    149 }
    150 
    151 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
    152                                       JITCodeEmitter &JCE) {
    153   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
    154   // writing?
    155   Subtarget.SetJITMode();
    156 
    157   // Machine code emitter pass for PowerPC.
    158   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
    159 
    160   return false;
    161 }
    162 
    163 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
    164   // Add first the target-independent BasicTTI pass, then our PPC pass. This
    165   // allows the PPC pass to delegate to the target independent layer when
    166   // appropriate.
    167   PM.add(createBasicTargetTransformInfoPass(this));
    168   PM.add(createPPCTargetTransformInfoPass(this));
    169 }
    170 
    171