| /external/llvm/lib/CodeGen/ |
| LiveRegMatrix.cpp | 75 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
77 << " to " << PrintReg(PhysReg, TRI) << ':');
79 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
80 MRI->setPhysRegUsed(PhysReg);
81 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
90 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
92 << " from " << PrintReg(PhysReg, TRI) << ':');
94 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
103 unsigned PhysReg) {
114 // The BitVector is indexed by PhysReg, not register unit
[all...] |
| RegAllocFast.cpp | 74 unsigned PhysReg; // Currently held here.
79 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
124 // Mark a physreg as used in this instruction.
125 void markRegUsedInInstr(unsigned PhysReg) {
126 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
130 // Check if a physreg or any of its aliases are used in this instruction.
131 bool isRegUsedInInstr(unsigned PhysReg) const {
132 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
178 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
179 unsigned calcSpillCost(unsigned PhysReg) const
[all...] |
| RegisterClassInfo.cpp | 98 unsigned PhysReg = RawOrder[i];
100 if (Reserved.test(PhysReg))
102 unsigned Cost = TRI->getCostPerUse(PhysReg);
105 if (CSRNum[PhysReg])
106 // PhysReg aliases a CSR, save it for later.
107 CSRAlias.push_back(PhysReg);
111 RCI.Order[N++] = PhysReg;
120 unsigned PhysReg = CSRAlias[i];
121 unsigned Cost = TRI->getCostPerUse(PhysReg);
124 RCI.Order[N++] = PhysReg;
[all...] |
| AllocationOrder.h | 79 /// Return true if PhysReg is a preferred register.
80 bool isHint(unsigned PhysReg) const {
81 return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
|
| InterferenceCache.h | 39 /// of PhysReg in all basic blocks.
41 /// PhysReg - The register currently represented.
42 unsigned PhysReg;
63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
86 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
97 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(nullptr), LIS(nullptr) {}
101 PhysReg = 0;
107 unsigned getPhysReg() const { return PhysReg; }
115 /// valid - Return true if this is a valid entry for physReg
[all...] |
| RegisterCoalescer.h | 57 /// is a physreg. This register class may be a super-register of both
66 /// Create a CoalescerPair representing a virtreg-to-physreg copy.
68 CoalescerPair(unsigned VirtReg, unsigned PhysReg,
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
|
| RegAllocGreedy.cpp | 248 unsigned PhysReg;
253 // Interference for PhysReg.
261 PhysReg = Reg;
281 /// Candidate info for each PhysReg in AllocationOrder.
338 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
343 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
365 unsigned PhysReg, unsigned &CostPerUseLimit,
572 unsigned PhysReg;
573 while ((PhysReg = Order.next()))
574 if (!Matrix->checkInterference(VirtReg, PhysReg))
[all...] |
| InterferenceCache.cpp | 55 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
56 unsigned E = PhysRegEntries[PhysReg];
57 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
73 Entries[E].reset(PhysReg, LIUArray, TRI, MF);
74 PhysRegEntries[PhysReg] = E;
88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
92 void InterferenceCache::Entry::reset(unsigned physReg,
99 PhysReg = physReg;
105 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
[all...] |
| RegAllocBasic.cpp | 112 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
164 // Spill or split all live virtual registers currently unified under PhysReg
167 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
174 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
186 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
190 // Spill each interfering vreg allocated to PhysReg or an alias.
228 while (unsigned PhysReg = Order.next()) {
229 // Check for interference in PhysReg
230 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
232 // PhysReg is available, allocate it
[all...] |
| VirtRegMap.cpp | 250 // assigned PhysReg must be marked as live-in to those blocks.
251 unsigned PhysReg = VRM->getPhys(VirtReg);
252 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
260 if (!LiveIn[i]->isLiveIn(PhysReg))
261 LiveIn[i]->addLiveIn(PhysReg);
327 // If we encounter a VirtReg or PhysReg then get at the PhysReg and add
328 // it to the physreg bitset. Later we use only the PhysRegs that were
339 unsigned PhysReg = VRM->getPhys(VirtReg);
340 assert(PhysReg != VirtRegMap::NO_PHYS_REG &
[all...] |
| LiveRangeCalc.h | 113 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
115 SlotIndex Kill, unsigned PhysReg);
162 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
163 void extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg = 0);
|
| LiveRangeCalc.cpp | 134 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg) {
150 if (findReachingDefs(LR, *KillMBB, Kill, PhysReg))
170 SlotIndex Kill, unsigned PhysReg) {
190 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
191 !MBB->isLiveIn(PhysReg)) {
|
| MachineRegisterInfo.cpp | 32 // Create the physreg use/def lists.
112 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
406 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
408 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
412 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
|
| MachineBasicBlock.cpp | 352 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) {
354 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
357 "Only the entry block and landing pads can have physreg live ins");
359 bool LiveIn = isLiveIn(PhysReg);
367 if (I->getOperand(1).getReg() == PhysReg) {
377 .addReg(PhysReg, RegState::Kill);
379 addLiveIn(PhysReg);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveRegMatrix.h | 20 // in the physreg.
86 /// assigned to PhysReg or its aliases. This interference could be resolved
96 /// regmask operand that doesn't preserve PhysReg. This typically means
97 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
101 /// Check for interference before assigning VirtReg to PhysReg.
102 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
105 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
107 /// Assign VirtReg to PhysReg.
109 /// update VirtRegMap. The live range is expected to be available in PhysReg.
110 void assign(LiveInterval &VirtReg, unsigned PhysReg);
[all...] |
| RegisterClassInfo.h | 108 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
109 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
110 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
111 if (unsigned N = CSRNum[PhysReg])
|
| MachineOperand.h | 467 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
471 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
473 assert(PhysReg < (1u << 30) && "Not a physical register");
474 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
477 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
478 bool clobbersPhysReg(unsigned PhysReg) const {
479 return clobbersPhysReg(getRegMask(), PhysReg);
666 /// mask has a bit set for each physreg that is preserved by this
670 /// Any physreg with a 0 bit in the mask is clobbered by the instruction
[all...] |
| MachineRegisterInfo.h | 540 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
542 /// a physreg.
543 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
594 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
696 /// canReserveReg - Returns true if PhysReg can be used as a reserved
699 bool canReserveReg(unsigned PhysReg) const {
700 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
713 /// isReserved - Returns true when PhysReg is a reserved register.
718 bool isReserved(unsigned PhysReg) const {
719 return getReservedRegs().test(PhysReg);
[all...] |
| MachineBasicBlock.h | 322 /// Add PhysReg as live in to this block, and ensure that there is a copy of
323 /// PhysReg to a virtual register of class RC. Return the virtual register
324 /// that is a copy of the live in PhysReg.
325 unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
|
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 407 std::string PhysReg;
410 return PhysReg;
414 return PhysReg;
416 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue())
418 PhysReg += "::";
419 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
420 return PhysReg;
523 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
524 if (PhysReg.empty()) {
534 PhysRegInputs->push_back(PhysReg);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 114 unsigned &PhysReg, int &Cost) {
127 PhysReg = Reg;
474 unsigned PhysReg = 0;
477 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
478 assert((PhysReg == 0 || !isChain) &&
479 "Chain dependence via physreg data?");
486 PhysReg = 0;
495 : SDep(OpSU, SDep::Data, PhysReg);
[all...] |
| FunctionLoweringInfo.cpp | 129 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
132 if (PhysReg.first == SP)
|
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 373 struct PhysRegOp PhysReg;
696 return PhysReg.Num;
880 OS << "PhysReg<" << PhysReg.Num << ">";
[all...] |
