/external/llvm/lib/Target/Hexagon/ |
HexagonCallingConvLower.h | 109 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { 111 if (!isAllocated(Regs[i])) 136 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { 137 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 142 unsigned Reg = Regs[FirstUnalloc]; 148 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, 150 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 155 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
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/external/llvm/include/llvm/CodeGen/ |
CallingConvLower.h | 300 unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const { 302 if (!isAllocated(Regs[i])) 327 unsigned AllocateReg(const MCPhysReg *Regs, unsigned NumRegs) { 328 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 333 unsigned Reg = Regs[FirstUnalloc]; 341 unsigned AllocateRegBlock(const uint16_t *Regs, unsigned NumRegs, unsigned RegsRequired) { 344 // Check for already-allocated regs in this block 346 if (isAllocated(Regs[StartIdx + BlockIdx])) { 354 MarkAllocated(Regs[StartIdx + BlockIdx]); 356 return Regs[StartIdx] [all...] |
RegisterScavenging.h | 180 void setUsed(BitVector &Regs) { 181 RegsAvailable.reset(Regs); 183 void setUnused(BitVector &Regs) { 184 RegsAvailable |= Regs;
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RegisterPressure.h | 305 void addLiveRegs(ArrayRef<unsigned> Regs); 430 void increaseRegPressure(ArrayRef<unsigned> Regs); 431 void decreaseRegPressure(ArrayRef<unsigned> Regs);
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/external/llvm/utils/TableGen/ |
RegisterInfoEmitter.cpp | 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor); 59 const std::vector<CodeGenRegister*> &Regs, 74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 171 const CodeGenRegister::Set &Regs = RC.getMembers(); 172 if (Regs.empty()) 177 OS << " {" << (*Regs.begin())->getWeight(RegBank) 315 const std::vector<CodeGenRegister*> &Regs, 323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 324 Record *Reg = Regs[i]->TheDef; 342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace") [all...] |
CodeGenRegisters.cpp | 159 RegUnitIterator(const CodeGenRegister::Set &Regs): 160 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { 349 // SR is composed of multiple sub-regs. Find their names in this register. [all...] |
CodeGenTarget.cpp | 226 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); 227 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); 228 if (I == Regs.end())
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CodeGenRegisters.h | 668 // Compute the set of registers completely covered by the registers in Regs. 669 // The returned BitVector will have a bit set for each register in Regs, 671 // registers in Regs. 675 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
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AsmMatcherEmitter.cpp | [all...] |
/external/llvm/lib/Target/SystemZ/Disassembler/ |
SystemZDisassembler.cpp | 52 const unsigned *Regs) { 54 RegNo = Regs[RegNo]; 190 const unsigned *Regs) { 194 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 200 const unsigned *Regs) { 204 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 210 const unsigned *Regs) { 215 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 217 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); 222 const unsigned *Regs) { [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
DbgValueHistoryCalculator.cpp | 114 // \brief Collect all registers clobbered by @MI and insert them to @Regs. 117 std::set<unsigned> &Regs) { 122 Regs.insert(*AI); 151 std::set<unsigned> &Regs) { 158 collectClobberedRegisters(MI, TRI, Regs);
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/external/llvm/lib/Target/SystemZ/AsmParser/ |
SystemZAsmParser.cpp | 313 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, 317 RegisterGroup Group, const unsigned *Regs, 322 const unsigned *Regs, RegisterKind RegKind); 325 const unsigned *Regs, RegisterKind RegKind, 456 // Parse a register of group Group. If Regs is nonnull, use it to map 461 const unsigned *Regs, bool IsAddress) { 466 if (Regs && Regs[Reg.Num] == 0) 470 if (Regs) 471 Reg.Num = Regs[Reg.Num] [all...] |
/external/llvm/lib/CodeGen/ |
ExecutionDepsFix.cpp | 644 SmallVector<LiveReg, 4> Regs; 655 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end(); 659 Regs.insert(i, LR); 663 Regs.push_back(LR); 669 while (!Regs.empty()) { 671 dv = Regs.pop_back_val().Value; 678 DomainValue *Latest = Regs.pop_back_val().Value;
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AggressiveAntiDepBreaker.h | 97 std::vector<unsigned> &Regs,
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AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs, 76 Regs.push_back(Reg); 155 // Examine the live-in regs of all successors. 548 std::vector<unsigned> Regs; 549 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); 550 assert(Regs.size() > 0 && "Empty register group!"); 551 if (Regs.size() == 0) 561 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 562 unsigned Reg = Regs[i]; 566 // If Reg has any references, then collect possible rename regs [all...] |
RegisterPressure.cpp | 423 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { 424 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 425 if (LiveRegs.insert(Regs[i])) 426 increaseRegPressure(Regs[i]); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelDAGToDAG.cpp | 831 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { 837 return createTuple(Regs, RegClassIDs, SubRegs); 840 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { 846 return createTuple(Regs, RegClassIDs, SubRegs); 849 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, 854 if (Regs.size() == 1) 855 return Regs[0]; 857 assert(Regs.size() >= 2 && Regs.size() <= 4); 859 SDLoc DL(Regs[0].getNode()) [all...] |
/external/llvm/lib/Target/ARM/ |
ARMFrameLowering.cpp | 811 SmallVector<std::pair<unsigned,bool>, 4> Regs; [all...] |
ARMLoadStoreOptimizer.cpp | 108 ArrayRef<std::pair<unsigned, bool> > Regs, 410 /// registers in Regs as the register operands that would be loaded / stored. 418 ArrayRef<std::pair<unsigned, bool> > Regs, 421 unsigned NumRegs = Regs.size(); 452 NewBase = Regs[NumRegs-1].first; 510 if (Base == Regs[I].first) { 542 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) 543 | getKillRegState(Regs[i].second)); 638 SmallVector<std::pair<unsigned, bool>, 8> Regs; 646 Regs.push_back(std::make_pair(Reg, isKill)) [all...] |
Thumb2SizeReduction.cpp | 214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) 215 if (*Regs == ARM::CPSR) 646 // Early exit if the regs aren't all low regs. [all...] |
/external/llvm/lib/Transforms/Scalar/ |
LoopStrengthReduce.cpp | 895 SmallPtrSet<const SCEV *, 16> &Regs, 908 SmallPtrSet<const SCEV *, 16> &Regs, 912 SmallPtrSet<const SCEV *, 16> &Regs, [all...] |
/external/llvm/lib/Target/PowerPC/Disassembler/ |
PPCDisassembler.cpp | 173 const unsigned (&Regs)[N]) { 175 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
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/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.cpp | 601 /// Regs - This list holds the registers assigned to the values. 605 SmallVector<unsigned, 4> Regs; 609 RegsForValue(const SmallVector<unsigned, 4> ®s, 611 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 622 Regs.push_back(Reg + i); 632 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 689 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT) [all...] |
/external/llvm/lib/Target/R600/ |
SIISelLowering.cpp | 435 SmallVector<SDValue, 4> Regs; 436 Regs.push_back(Val); 440 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT)); 446 Regs.push_back(DAG.getUNDEF(VT)); 448 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs)); [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |