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      1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
     11 #include "llvm/ADT/STLExtras.h"
     12 #include "llvm/MC/MCContext.h"
     13 #include "llvm/MC/MCExpr.h"
     14 #include "llvm/MC/MCInst.h"
     15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
     16 #include "llvm/MC/MCStreamer.h"
     17 #include "llvm/MC/MCSubtargetInfo.h"
     18 #include "llvm/MC/MCTargetAsmParser.h"
     19 #include "llvm/Support/TargetRegistry.h"
     20 
     21 using namespace llvm;
     22 
     23 // Return true if Expr is in the range [MinValue, MaxValue].
     24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
     25   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
     26     int64_t Value = CE->getValue();
     27     return Value >= MinValue && Value <= MaxValue;
     28   }
     29   return false;
     30 }
     31 
     32 namespace {
     33 enum RegisterKind {
     34   GR32Reg,
     35   GRH32Reg,
     36   GR64Reg,
     37   GR128Reg,
     38   ADDR32Reg,
     39   ADDR64Reg,
     40   FP32Reg,
     41   FP64Reg,
     42   FP128Reg
     43 };
     44 
     45 enum MemoryKind {
     46   BDMem,
     47   BDXMem,
     48   BDLMem
     49 };
     50 
     51 class SystemZOperand : public MCParsedAsmOperand {
     52 public:
     53 private:
     54   enum OperandKind {
     55     KindInvalid,
     56     KindToken,
     57     KindReg,
     58     KindAccessReg,
     59     KindImm,
     60     KindMem
     61   };
     62 
     63   OperandKind Kind;
     64   SMLoc StartLoc, EndLoc;
     65 
     66   // A string of length Length, starting at Data.
     67   struct TokenOp {
     68     const char *Data;
     69     unsigned Length;
     70   };
     71 
     72   // LLVM register Num, which has kind Kind.  In some ways it might be
     73   // easier for this class to have a register bank (general, floating-point
     74   // or access) and a raw register number (0-15).  This would postpone the
     75   // interpretation of the operand to the add*() methods and avoid the need
     76   // for context-dependent parsing.  However, we do things the current way
     77   // because of the virtual getReg() method, which needs to distinguish
     78   // between (say) %r0 used as a single register and %r0 used as a pair.
     79   // Context-dependent parsing can also give us slightly better error
     80   // messages when invalid pairs like %r1 are used.
     81   struct RegOp {
     82     RegisterKind Kind;
     83     unsigned Num;
     84   };
     85 
     86   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
     87   // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
     88   // Length is the operand length for D(L,B)-style operands, otherwise
     89   // it is null.
     90   struct MemOp {
     91     unsigned Base : 8;
     92     unsigned Index : 8;
     93     unsigned RegKind : 8;
     94     unsigned Unused : 8;
     95     const MCExpr *Disp;
     96     const MCExpr *Length;
     97   };
     98 
     99   union {
    100     TokenOp Token;
    101     RegOp Reg;
    102     unsigned AccessReg;
    103     const MCExpr *Imm;
    104     MemOp Mem;
    105   };
    106 
    107   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
    108     // Add as immediates when possible.  Null MCExpr = 0.
    109     if (!Expr)
    110       Inst.addOperand(MCOperand::CreateImm(0));
    111     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
    112       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
    113     else
    114       Inst.addOperand(MCOperand::CreateExpr(Expr));
    115   }
    116 
    117 public:
    118   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
    119       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
    120 
    121   // Create particular kinds of operand.
    122   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
    123                                                        SMLoc EndLoc) {
    124     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
    125   }
    126   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
    127     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
    128     Op->Token.Data = Str.data();
    129     Op->Token.Length = Str.size();
    130     return Op;
    131   }
    132   static std::unique_ptr<SystemZOperand>
    133   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
    134     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
    135     Op->Reg.Kind = Kind;
    136     Op->Reg.Num = Num;
    137     return Op;
    138   }
    139   static std::unique_ptr<SystemZOperand>
    140   createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
    141     auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
    142     Op->AccessReg = Num;
    143     return Op;
    144   }
    145   static std::unique_ptr<SystemZOperand>
    146   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
    147     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
    148     Op->Imm = Expr;
    149     return Op;
    150   }
    151   static std::unique_ptr<SystemZOperand>
    152   createMem(RegisterKind RegKind, unsigned Base, const MCExpr *Disp,
    153             unsigned Index, const MCExpr *Length, SMLoc StartLoc,
    154             SMLoc EndLoc) {
    155     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
    156     Op->Mem.RegKind = RegKind;
    157     Op->Mem.Base = Base;
    158     Op->Mem.Index = Index;
    159     Op->Mem.Disp = Disp;
    160     Op->Mem.Length = Length;
    161     return Op;
    162   }
    163 
    164   // Token operands
    165   bool isToken() const override {
    166     return Kind == KindToken;
    167   }
    168   StringRef getToken() const {
    169     assert(Kind == KindToken && "Not a token");
    170     return StringRef(Token.Data, Token.Length);
    171   }
    172 
    173   // Register operands.
    174   bool isReg() const override {
    175     return Kind == KindReg;
    176   }
    177   bool isReg(RegisterKind RegKind) const {
    178     return Kind == KindReg && Reg.Kind == RegKind;
    179   }
    180   unsigned getReg() const override {
    181     assert(Kind == KindReg && "Not a register");
    182     return Reg.Num;
    183   }
    184 
    185   // Access register operands.  Access registers aren't exposed to LLVM
    186   // as registers.
    187   bool isAccessReg() const {
    188     return Kind == KindAccessReg;
    189   }
    190 
    191   // Immediate operands.
    192   bool isImm() const override {
    193     return Kind == KindImm;
    194   }
    195   bool isImm(int64_t MinValue, int64_t MaxValue) const {
    196     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
    197   }
    198   const MCExpr *getImm() const {
    199     assert(Kind == KindImm && "Not an immediate");
    200     return Imm;
    201   }
    202 
    203   // Memory operands.
    204   bool isMem() const override {
    205     return Kind == KindMem;
    206   }
    207   bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
    208     return (Kind == KindMem &&
    209             Mem.RegKind == RegKind &&
    210             (MemKind == BDXMem || !Mem.Index) &&
    211             (MemKind == BDLMem) == (Mem.Length != nullptr));
    212   }
    213   bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
    214     return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
    215   }
    216   bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
    217     return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
    218   }
    219   bool isMemDisp12Len8(RegisterKind RegKind) const {
    220     return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
    221   }
    222 
    223   // Override MCParsedAsmOperand.
    224   SMLoc getStartLoc() const override { return StartLoc; }
    225   SMLoc getEndLoc() const override { return EndLoc; }
    226   void print(raw_ostream &OS) const override;
    227 
    228   // Used by the TableGen code to add particular types of operand
    229   // to an instruction.
    230   void addRegOperands(MCInst &Inst, unsigned N) const {
    231     assert(N == 1 && "Invalid number of operands");
    232     Inst.addOperand(MCOperand::CreateReg(getReg()));
    233   }
    234   void addAccessRegOperands(MCInst &Inst, unsigned N) const {
    235     assert(N == 1 && "Invalid number of operands");
    236     assert(Kind == KindAccessReg && "Invalid operand type");
    237     Inst.addOperand(MCOperand::CreateImm(AccessReg));
    238   }
    239   void addImmOperands(MCInst &Inst, unsigned N) const {
    240     assert(N == 1 && "Invalid number of operands");
    241     addExpr(Inst, getImm());
    242   }
    243   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
    244     assert(N == 2 && "Invalid number of operands");
    245     assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
    246     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
    247     addExpr(Inst, Mem.Disp);
    248   }
    249   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
    250     assert(N == 3 && "Invalid number of operands");
    251     assert(Kind == KindMem && "Invalid operand type");
    252     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
    253     addExpr(Inst, Mem.Disp);
    254     Inst.addOperand(MCOperand::CreateReg(Mem.Index));
    255   }
    256   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
    257     assert(N == 3 && "Invalid number of operands");
    258     assert(Kind == KindMem && "Invalid operand type");
    259     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
    260     addExpr(Inst, Mem.Disp);
    261     addExpr(Inst, Mem.Length);
    262   }
    263 
    264   // Used by the TableGen code to check for particular operand types.
    265   bool isGR32() const { return isReg(GR32Reg); }
    266   bool isGRH32() const { return isReg(GRH32Reg); }
    267   bool isGRX32() const { return false; }
    268   bool isGR64() const { return isReg(GR64Reg); }
    269   bool isGR128() const { return isReg(GR128Reg); }
    270   bool isADDR32() const { return isReg(ADDR32Reg); }
    271   bool isADDR64() const { return isReg(ADDR64Reg); }
    272   bool isADDR128() const { return false; }
    273   bool isFP32() const { return isReg(FP32Reg); }
    274   bool isFP64() const { return isReg(FP64Reg); }
    275   bool isFP128() const { return isReg(FP128Reg); }
    276   bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); }
    277   bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); }
    278   bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); }
    279   bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); }
    280   bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); }
    281   bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); }
    282   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
    283   bool isU4Imm() const { return isImm(0, 15); }
    284   bool isU6Imm() const { return isImm(0, 63); }
    285   bool isU8Imm() const { return isImm(0, 255); }
    286   bool isS8Imm() const { return isImm(-128, 127); }
    287   bool isU16Imm() const { return isImm(0, 65535); }
    288   bool isS16Imm() const { return isImm(-32768, 32767); }
    289   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
    290   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
    291 };
    292 
    293 class SystemZAsmParser : public MCTargetAsmParser {
    294 #define GET_ASSEMBLER_HEADER
    295 #include "SystemZGenAsmMatcher.inc"
    296 
    297 private:
    298   MCSubtargetInfo &STI;
    299   MCAsmParser &Parser;
    300   enum RegisterGroup {
    301     RegGR,
    302     RegFP,
    303     RegAccess
    304   };
    305   struct Register {
    306     RegisterGroup Group;
    307     unsigned Num;
    308     SMLoc StartLoc, EndLoc;
    309   };
    310 
    311   bool parseRegister(Register &Reg);
    312 
    313   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
    314                      bool IsAddress = false);
    315 
    316   OperandMatchResultTy parseRegister(OperandVector &Operands,
    317                                      RegisterGroup Group, const unsigned *Regs,
    318                                      RegisterKind Kind);
    319 
    320   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
    321                     unsigned &Index, const MCExpr *&Length,
    322                     const unsigned *Regs, RegisterKind RegKind);
    323 
    324   OperandMatchResultTy parseAddress(OperandVector &Operands,
    325                                     const unsigned *Regs, RegisterKind RegKind,
    326                                     MemoryKind MemKind);
    327 
    328   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
    329 
    330 public:
    331   SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
    332                    const MCInstrInfo &MII,
    333                    const MCTargetOptions &Options)
    334       : MCTargetAsmParser(), STI(sti), Parser(parser) {
    335     MCAsmParserExtension::Initialize(Parser);
    336 
    337     // Initialize the set of available features.
    338     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
    339   }
    340 
    341   // Override MCTargetAsmParser.
    342   bool ParseDirective(AsmToken DirectiveID) override;
    343   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
    344   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
    345                         SMLoc NameLoc, OperandVector &Operands) override;
    346   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
    347                                OperandVector &Operands, MCStreamer &Out,
    348                                unsigned &ErrorInfo,
    349                                bool MatchingInlineAsm) override;
    350 
    351   // Used by the TableGen code to parse particular operand types.
    352   OperandMatchResultTy parseGR32(OperandVector &Operands) {
    353     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
    354   }
    355   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
    356     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
    357   }
    358   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
    359     llvm_unreachable("GRX32 should only be used for pseudo instructions");
    360   }
    361   OperandMatchResultTy parseGR64(OperandVector &Operands) {
    362     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
    363   }
    364   OperandMatchResultTy parseGR128(OperandVector &Operands) {
    365     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
    366   }
    367   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
    368     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
    369   }
    370   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
    371     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
    372   }
    373   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
    374     llvm_unreachable("Shouldn't be used as an operand");
    375   }
    376   OperandMatchResultTy parseFP32(OperandVector &Operands) {
    377     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
    378   }
    379   OperandMatchResultTy parseFP64(OperandVector &Operands) {
    380     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
    381   }
    382   OperandMatchResultTy parseFP128(OperandVector &Operands) {
    383     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
    384   }
    385   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
    386     return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem);
    387   }
    388   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
    389     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem);
    390   }
    391   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
    392     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem);
    393   }
    394   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
    395     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem);
    396   }
    397   OperandMatchResultTy parseAccessReg(OperandVector &Operands);
    398   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
    399                                   int64_t MaxVal);
    400   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
    401     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1);
    402   }
    403   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
    404     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1);
    405   }
    406 };
    407 } // end anonymous namespace
    408 
    409 #define GET_REGISTER_MATCHER
    410 #define GET_SUBTARGET_FEATURE_NAME
    411 #define GET_MATCHER_IMPLEMENTATION
    412 #include "SystemZGenAsmMatcher.inc"
    413 
    414 void SystemZOperand::print(raw_ostream &OS) const {
    415   llvm_unreachable("Not implemented");
    416 }
    417 
    418 // Parse one register of the form %<prefix><number>.
    419 bool SystemZAsmParser::parseRegister(Register &Reg) {
    420   Reg.StartLoc = Parser.getTok().getLoc();
    421 
    422   // Eat the % prefix.
    423   if (Parser.getTok().isNot(AsmToken::Percent))
    424     return Error(Parser.getTok().getLoc(), "register expected");
    425   Parser.Lex();
    426 
    427   // Expect a register name.
    428   if (Parser.getTok().isNot(AsmToken::Identifier))
    429     return Error(Reg.StartLoc, "invalid register");
    430 
    431   // Check that there's a prefix.
    432   StringRef Name = Parser.getTok().getString();
    433   if (Name.size() < 2)
    434     return Error(Reg.StartLoc, "invalid register");
    435   char Prefix = Name[0];
    436 
    437   // Treat the rest of the register name as a register number.
    438   if (Name.substr(1).getAsInteger(10, Reg.Num))
    439     return Error(Reg.StartLoc, "invalid register");
    440 
    441   // Look for valid combinations of prefix and number.
    442   if (Prefix == 'r' && Reg.Num < 16)
    443     Reg.Group = RegGR;
    444   else if (Prefix == 'f' && Reg.Num < 16)
    445     Reg.Group = RegFP;
    446   else if (Prefix == 'a' && Reg.Num < 16)
    447     Reg.Group = RegAccess;
    448   else
    449     return Error(Reg.StartLoc, "invalid register");
    450 
    451   Reg.EndLoc = Parser.getTok().getLoc();
    452   Parser.Lex();
    453   return false;
    454 }
    455 
    456 // Parse a register of group Group.  If Regs is nonnull, use it to map
    457 // the raw register number to LLVM numbering, with zero entries indicating
    458 // an invalid register.  IsAddress says whether the register appears in an
    459 // address context.
    460 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
    461                                      const unsigned *Regs, bool IsAddress) {
    462   if (parseRegister(Reg))
    463     return true;
    464   if (Reg.Group != Group)
    465     return Error(Reg.StartLoc, "invalid operand for instruction");
    466   if (Regs && Regs[Reg.Num] == 0)
    467     return Error(Reg.StartLoc, "invalid register pair");
    468   if (Reg.Num == 0 && IsAddress)
    469     return Error(Reg.StartLoc, "%r0 used in an address");
    470   if (Regs)
    471     Reg.Num = Regs[Reg.Num];
    472   return false;
    473 }
    474 
    475 // Parse a register and add it to Operands.  The other arguments are as above.
    476 SystemZAsmParser::OperandMatchResultTy
    477 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
    478                                 const unsigned *Regs, RegisterKind Kind) {
    479   if (Parser.getTok().isNot(AsmToken::Percent))
    480     return MatchOperand_NoMatch;
    481 
    482   Register Reg;
    483   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
    484   if (parseRegister(Reg, Group, Regs, IsAddress))
    485     return MatchOperand_ParseFail;
    486 
    487   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
    488                                                Reg.StartLoc, Reg.EndLoc));
    489   return MatchOperand_Success;
    490 }
    491 
    492 // Parse a memory operand into Base, Disp, Index and Length.
    493 // Regs maps asm register numbers to LLVM register numbers and RegKind
    494 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
    495 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
    496                                     unsigned &Index, const MCExpr *&Length,
    497                                     const unsigned *Regs,
    498                                     RegisterKind RegKind) {
    499   // Parse the displacement, which must always be present.
    500   if (getParser().parseExpression(Disp))
    501     return true;
    502 
    503   // Parse the optional base and index.
    504   Index = 0;
    505   Base = 0;
    506   Length = nullptr;
    507   if (getLexer().is(AsmToken::LParen)) {
    508     Parser.Lex();
    509 
    510     if (getLexer().is(AsmToken::Percent)) {
    511       // Parse the first register and decide whether it's a base or an index.
    512       Register Reg;
    513       if (parseRegister(Reg, RegGR, Regs, RegKind))
    514         return true;
    515       if (getLexer().is(AsmToken::Comma))
    516         Index = Reg.Num;
    517       else
    518         Base = Reg.Num;
    519     } else {
    520       // Parse the length.
    521       if (getParser().parseExpression(Length))
    522         return true;
    523     }
    524 
    525     // Check whether there's a second register.  It's the base if so.
    526     if (getLexer().is(AsmToken::Comma)) {
    527       Parser.Lex();
    528       Register Reg;
    529       if (parseRegister(Reg, RegGR, Regs, RegKind))
    530         return true;
    531       Base = Reg.Num;
    532     }
    533 
    534     // Consume the closing bracket.
    535     if (getLexer().isNot(AsmToken::RParen))
    536       return Error(Parser.getTok().getLoc(), "unexpected token in address");
    537     Parser.Lex();
    538   }
    539   return false;
    540 }
    541 
    542 // Parse a memory operand and add it to Operands.  The other arguments
    543 // are as above.
    544 SystemZAsmParser::OperandMatchResultTy
    545 SystemZAsmParser::parseAddress(OperandVector &Operands, const unsigned *Regs,
    546                                RegisterKind RegKind, MemoryKind MemKind) {
    547   SMLoc StartLoc = Parser.getTok().getLoc();
    548   unsigned Base, Index;
    549   const MCExpr *Disp;
    550   const MCExpr *Length;
    551   if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
    552     return MatchOperand_ParseFail;
    553 
    554   if (Index && MemKind != BDXMem)
    555     {
    556       Error(StartLoc, "invalid use of indexed addressing");
    557       return MatchOperand_ParseFail;
    558     }
    559 
    560   if (Length && MemKind != BDLMem)
    561     {
    562       Error(StartLoc, "invalid use of length addressing");
    563       return MatchOperand_ParseFail;
    564     }
    565 
    566   if (!Length && MemKind == BDLMem)
    567     {
    568       Error(StartLoc, "missing length in address");
    569       return MatchOperand_ParseFail;
    570     }
    571 
    572   SMLoc EndLoc =
    573     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    574   Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
    575                                                Length, StartLoc, EndLoc));
    576   return MatchOperand_Success;
    577 }
    578 
    579 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
    580   return true;
    581 }
    582 
    583 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
    584                                      SMLoc &EndLoc) {
    585   Register Reg;
    586   if (parseRegister(Reg))
    587     return true;
    588   if (Reg.Group == RegGR)
    589     RegNo = SystemZMC::GR64Regs[Reg.Num];
    590   else if (Reg.Group == RegFP)
    591     RegNo = SystemZMC::FP64Regs[Reg.Num];
    592   else
    593     // FIXME: Access registers aren't modelled as LLVM registers yet.
    594     return Error(Reg.StartLoc, "invalid operand for instruction");
    595   StartLoc = Reg.StartLoc;
    596   EndLoc = Reg.EndLoc;
    597   return false;
    598 }
    599 
    600 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
    601                                         StringRef Name, SMLoc NameLoc,
    602                                         OperandVector &Operands) {
    603   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
    604 
    605   // Read the remaining operands.
    606   if (getLexer().isNot(AsmToken::EndOfStatement)) {
    607     // Read the first operand.
    608     if (parseOperand(Operands, Name)) {
    609       Parser.eatToEndOfStatement();
    610       return true;
    611     }
    612 
    613     // Read any subsequent operands.
    614     while (getLexer().is(AsmToken::Comma)) {
    615       Parser.Lex();
    616       if (parseOperand(Operands, Name)) {
    617         Parser.eatToEndOfStatement();
    618         return true;
    619       }
    620     }
    621     if (getLexer().isNot(AsmToken::EndOfStatement)) {
    622       SMLoc Loc = getLexer().getLoc();
    623       Parser.eatToEndOfStatement();
    624       return Error(Loc, "unexpected token in argument list");
    625     }
    626   }
    627 
    628   // Consume the EndOfStatement.
    629   Parser.Lex();
    630   return false;
    631 }
    632 
    633 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
    634                                     StringRef Mnemonic) {
    635   // Check if the current operand has a custom associated parser, if so, try to
    636   // custom parse the operand, or fallback to the general approach.
    637   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
    638   if (ResTy == MatchOperand_Success)
    639     return false;
    640 
    641   // If there wasn't a custom match, try the generic matcher below. Otherwise,
    642   // there was a match, but an error occurred, in which case, just return that
    643   // the operand parsing failed.
    644   if (ResTy == MatchOperand_ParseFail)
    645     return true;
    646 
    647   // Check for a register.  All real register operands should have used
    648   // a context-dependent parse routine, which gives the required register
    649   // class.  The code is here to mop up other cases, like those where
    650   // the instruction isn't recognized.
    651   if (Parser.getTok().is(AsmToken::Percent)) {
    652     Register Reg;
    653     if (parseRegister(Reg))
    654       return true;
    655     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
    656     return false;
    657   }
    658 
    659   // The only other type of operand is an immediate or address.  As above,
    660   // real address operands should have used a context-dependent parse routine,
    661   // so we treat any plain expression as an immediate.
    662   SMLoc StartLoc = Parser.getTok().getLoc();
    663   unsigned Base, Index;
    664   const MCExpr *Expr, *Length;
    665   if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
    666     return true;
    667 
    668   SMLoc EndLoc =
    669     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    670   if (Base || Index || Length)
    671     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
    672   else
    673     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
    674   return false;
    675 }
    676 
    677 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
    678                                                OperandVector &Operands,
    679                                                MCStreamer &Out,
    680                                                unsigned &ErrorInfo,
    681                                                bool MatchingInlineAsm) {
    682   MCInst Inst;
    683   unsigned MatchResult;
    684 
    685   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
    686                                      MatchingInlineAsm);
    687   switch (MatchResult) {
    688   default: break;
    689   case Match_Success:
    690     Inst.setLoc(IDLoc);
    691     Out.EmitInstruction(Inst, STI);
    692     return false;
    693 
    694   case Match_MissingFeature: {
    695     assert(ErrorInfo && "Unknown missing feature!");
    696     // Special case the error message for the very common case where only
    697     // a single subtarget feature is missing
    698     std::string Msg = "instruction requires:";
    699     unsigned Mask = 1;
    700     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
    701       if (ErrorInfo & Mask) {
    702         Msg += " ";
    703         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
    704       }
    705       Mask <<= 1;
    706     }
    707     return Error(IDLoc, Msg);
    708   }
    709 
    710   case Match_InvalidOperand: {
    711     SMLoc ErrorLoc = IDLoc;
    712     if (ErrorInfo != ~0U) {
    713       if (ErrorInfo >= Operands.size())
    714         return Error(IDLoc, "too few operands for instruction");
    715 
    716       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
    717       if (ErrorLoc == SMLoc())
    718         ErrorLoc = IDLoc;
    719     }
    720     return Error(ErrorLoc, "invalid operand for instruction");
    721   }
    722 
    723   case Match_MnemonicFail:
    724     return Error(IDLoc, "invalid instruction");
    725   }
    726 
    727   llvm_unreachable("Unexpected match type");
    728 }
    729 
    730 SystemZAsmParser::OperandMatchResultTy
    731 SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
    732   if (Parser.getTok().isNot(AsmToken::Percent))
    733     return MatchOperand_NoMatch;
    734 
    735   Register Reg;
    736   if (parseRegister(Reg, RegAccess, nullptr))
    737     return MatchOperand_ParseFail;
    738 
    739   Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
    740                                                      Reg.StartLoc,
    741                                                      Reg.EndLoc));
    742   return MatchOperand_Success;
    743 }
    744 
    745 SystemZAsmParser::OperandMatchResultTy
    746 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
    747                              int64_t MaxVal) {
    748   MCContext &Ctx = getContext();
    749   MCStreamer &Out = getStreamer();
    750   const MCExpr *Expr;
    751   SMLoc StartLoc = Parser.getTok().getLoc();
    752   if (getParser().parseExpression(Expr))
    753     return MatchOperand_NoMatch;
    754 
    755   // For consistency with the GNU assembler, treat immediates as offsets
    756   // from ".".
    757   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
    758     int64_t Value = CE->getValue();
    759     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
    760       Error(StartLoc, "offset out of range");
    761       return MatchOperand_ParseFail;
    762     }
    763     MCSymbol *Sym = Ctx.CreateTempSymbol();
    764     Out.EmitLabel(Sym);
    765     const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
    766                                                  Ctx);
    767     Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
    768   }
    769 
    770   SMLoc EndLoc =
    771     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    772   Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
    773   return MatchOperand_Success;
    774 }
    775 
    776 // Force static initialization.
    777 extern "C" void LLVMInitializeSystemZAsmParser() {
    778   RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
    779 }
    780