/external/llvm/lib/Target/R600/ |
R600MachineScheduler.cpp | 375 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass); 378 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass); 381 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass); 384 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);
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SIFixSGPRCopies.cpp | 226 MRI.constrainRegClass(Reg, RC); 232 MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass);
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/external/llvm/lib/CodeGen/ |
OptimizePHIs.cpp | 170 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
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UnreachableBlockElim.cpp | 197 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
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MachineCSE.cpp | 152 if (!MRI->constrainRegClass(SrcReg, RC)) 554 if (!MRI->constrainRegClass(NewReg, OldRC)) {
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MachineRegisterInfo.cpp | 52 MachineRegisterInfo::constrainRegClass(unsigned Reg,
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TailDuplication.cpp | 299 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { 451 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg)); [all...] |
TwoAddressInstructionPass.cpp | [all...] |
PeepholeOptimizer.cpp | 388 MRI->constrainRegClass(DstReg, DstRC); [all...] |
MachineBasicBlock.cpp | 369 if (!MRI.constrainRegClass(VirtReg, RC)) [all...] |
MachineLICM.cpp | [all...] |
RegisterCoalescer.cpp | 647 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.cpp | 451 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); 457 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); 497 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { 501 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { 505 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { 508 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { 536 MRI.constrainRegClass(TrueReg, RC); 537 MRI.constrainRegClass(FalseReg, RC); 648 !MRI->constrainRegClass(Reg, OpRegCstraints)) [all...] |
AArch64ConditionalCompares.cpp | 604 MRI->constrainRegClass(HeadCond[2].getReg(), 651 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), 654 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
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AArch64RegisterInfo.cpp | 297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
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AArch64FastISel.cpp | 585 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass); 674 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass); 798 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass); [all...] |
/external/llvm/lib/Target/ARM/ |
Thumb2InstrInfo.cpp | 155 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); 196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
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A15SDOptimizer.cpp | 664 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
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ARMBaseRegisterInfo.cpp | 596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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ARMLoadStoreOptimizer.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
FastISel.cpp | [all...] |
InstrEmitter.cpp | 332 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 444 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineRegisterInfo.h | 514 /// constrainRegClass(ToReg, getRegClass(FromReg)) 564 /// constrainRegClass - Constrain the register class of the specified virtual 571 const TargetRegisterClass *constrainRegClass(unsigned Reg, [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZInstrInfo.cpp | 701 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass); 702 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass); [all...] |