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  /external/llvm/lib/Target/R600/
R600ClauseMergePass.cpp 98 CFAlu->getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
149 RootCFAlu->getOperand(Mode0Idx).setImm(
151 RootCFAlu->getOperand(KBank0Idx).setImm(
153 RootCFAlu->getOperand(KBank0LineIdx).setImm(
157 RootCFAlu->getOperand(Mode1Idx).setImm(
159 RootCFAlu->getOperand(KBank1Idx).setImm(
161 RootCFAlu->getOperand(KBank1LineIdx).setImm(
164 RootCFAlu->getOperand(CntIdx).setImm(CumuledInsts);
R600InstrInfo.cpp 801 PredSet->getOperand(2).setImm(Cond[1].getImm());
817 PredSet->getOperand(2).setImm(Cond[1].getImm());
970 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
973 MO.setImm(OPCODE_IS_ZERO_INT);
976 MO.setImm(OPCODE_IS_NOT_ZERO);
979 MO.setImm(OPCODE_IS_ZERO);
1019 MI->getOperand(8).setImm(0);
    [all...]
R600Packetizer.cpp 231 MI->getOperand(LastOp).setImm(Bit);
309 MI->getOperand(Op).setImm(BS[i]);
313 MI->getOperand(Op).setImm(BS.back());
R600ControlFlowFinalizer.cpp 428 ClauseHead->getOperand(7).setImm(ClauseContent.size() - 1);
448 Clause.first->getOperand(0).setImm(0);
460 MI->getOperand(0).setImm(Addr + MI->getOperand(0).getImm());
605 IfOrElseInst->getOperand(1).setImm(1);
AMDILCFGStructurizer.cpp 447 .setImm(OPCODE_IS_NOT_ZERO_INT);
451 .setImm(OPCODE_IS_ZERO_INT);
455 .setImm(OPCODE_IS_NOT_ZERO);
459 .setImm(OPCODE_IS_ZERO);
    [all...]
R600OptimizeVectorRegisters.cpp 257 MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600InstrInfo.cpp 277 PredSet->getOperand(2).setImm(Cond[1].getImm());
288 PredSet->getOperand(2).setImm(Cond[1].getImm());
409 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
412 MO.setImm(OPCODE_IS_ZERO_INT);
415 MO.setImm(OPCODE_IS_NOT_ZERO);
418 MO.setImm(OPCODE_IS_ZERO);
502 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
511 FlagOp.setImm(InstFlags);
  /external/mesa3d/src/gallium/drivers/radeon/
R600InstrInfo.cpp 277 PredSet->getOperand(2).setImm(Cond[1].getImm());
288 PredSet->getOperand(2).setImm(Cond[1].getImm());
409 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
412 MO.setImm(OPCODE_IS_ZERO_INT);
415 MO.setImm(OPCODE_IS_NOT_ZERO);
418 MO.setImm(OPCODE_IS_ZERO);
502 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
511 FlagOp.setImm(InstFlags);
  /external/llvm/include/llvm/MC/
MCInst.h 78 void setImm(int64_t Val) {
  /external/llvm/lib/Target/SystemZ/
SystemZShortenInst.cpp 94 MI.getOperand(1).setImm(Imm >> 16);
SystemZElimCompare.cpp 282 AlterMasks[I]->setImm(CCValues);
285 AlterMasks[I + 1]->setImm((CCMask & ReusableCCMask) |
SystemZInstrInfo.cpp 70 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
94 OffsetMO.setImm(Offset);
110 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
358 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
    [all...]
  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCCodeEmitter.cpp 64 Inst.getOperand(2).setImm(Shift);
105 InstIn.getOperand(2).setImm(pos - 32);
111 InstIn.getOperand(3).setImm(size - 32);
  /external/llvm/include/llvm/CodeGen/
MachineOperand.h 504 void setImm(int64_t immVal) {
544 /// the setImm method should be used.
560 Op.setImm(Val);
  /external/llvm/lib/Target/Mips/
MipsInstrInfo.cpp 179 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
  /external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 189 Cond[0].setImm(AArch64CC::getInvertedCondCode(CC));
196 Cond[1].setImm(AArch64::CBNZW);
199 Cond[1].setImm(AArch64::CBZW);
202 Cond[1].setImm(AArch64::CBNZX);
205 Cond[1].setImm(AArch64::CBZX);
208 Cond[1].setImm(AArch64::TBNZW);
211 Cond[1].setImm(AArch64::TBZW);
214 Cond[1].setImm(AArch64::TBNZX);
217 Cond[1].setImm(AArch64::TBZX);
    [all...]
AArch64BranchRelaxation.cpp 348 MI->getOperand(0).setImm((int64_t)CC);
  /external/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp 108 MO.setImm(MFI->getMaxCallFrameSize());
HexagonPeephole.cpp 329 Dst.setImm(Src.getImm());
HexagonVLIWPacketizer.cpp     [all...]
HexagonHardwareLoops.cpp     [all...]
  /external/llvm/lib/Target/MSP430/
MSP430InstrInfo.cpp 157 Cond[0].setImm(CC);
  /external/llvm/lib/Target/XCore/
XCoreInstrInfo.cpp 420 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 297 MI->getOperand(4).setImm((ME+1) & 31);
298 MI->getOperand(5).setImm((MB-1) & 31);
    [all...]
  /external/llvm/lib/Target/ARM/
Thumb2InstrInfo.cpp 87 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);

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