| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 194 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
195 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
206 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
211 { ISD::SHL, MVT::v8i32, 1 },
212 { ISD::SRL, MVT::v8i32, 1 },
213 { ISD::SRA, MVT::v8i32, 1 },
232 { ISD::SDIV, MVT::v8i32, 8*20 },
236 { ISD::UDIV, MVT::v8i32, 8*20 },
357 { ISD::MUL, MVT::v8i32, 4 },
358 { ISD::SUB, MVT::v8i32, 4 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 81 v8i32 = 35, // 8 x i32 enumerator in enum:llvm::MVT::SimpleValueType
220 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64);
290 case v8i32:
330 case v8i32:
418 case v8i32:
538 if (NumElements == 8) return MVT::v8i32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 225 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
226 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
236 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
256 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
257 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
405 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 153 case MVT::v8i32: return "v8i32";
221 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 106 DecodePSHUFMask(MVT::v8i32,
209 DecodeUNPCKHMask(MVT::v8i32, ShuffleMask);
282 DecodeUNPCKLMask(MVT::v8i32, ShuffleMask);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 49 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
86 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
89 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
96 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
163 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
179 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
[all...] |
| AMDGPUISelLowering.cpp | 149 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
195 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 452 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 * AmortizationCost },
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 94 case MVT::v8i32: return "MVT::v8i32";
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
|
