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    Searched refs:virtReg (Results 1 - 5 of 5) sorted by null

  /external/llvm/include/llvm/CodeGen/
VirtRegMap.h 92 bool hasPhys(unsigned virtReg) const {
93 return getPhys(virtReg) != NO_PHYS_REG;
98 unsigned getPhys(unsigned virtReg) const {
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
100 return Virt2PhysMap[virtReg];
105 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
106 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
108 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
111 Virt2PhysMap[virtReg] = physReg;
116 void clearVirt(unsigned virtReg) {
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LiveIntervalUnion.h 87 void unify(LiveInterval &VirtReg);
90 void extract(LiveInterval &VirtReg);
107 LiveInterval *VirtReg;
108 LiveInterval::iterator VirtRegI; // current position in VirtReg
117 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
120 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
126 VirtReg = nullptr;
137 if (UserTag == UTag && VirtReg == VReg &&
144 VirtReg = VReg;
149 LiveInterval &virtReg() const
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  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
SIAssignInterpRegs.cpp 39 unsigned physReg, unsigned virtReg);
124 unsigned physReg, unsigned virtReg)
128 MRI.addLiveIn(physReg, virtReg);
131 TII->get(TargetOpcode::COPY), virtReg)
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
  /external/mesa3d/src/gallium/drivers/radeon/
SIAssignInterpRegs.cpp 39 unsigned physReg, unsigned virtReg);
124 unsigned physReg, unsigned virtReg)
128 MRI.addLiveIn(physReg, virtReg);
131 TII->get(TargetOpcode::COPY), virtReg)
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
  /external/llvm/lib/CodeGen/
VirtRegMap.cpp 83 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
84 unsigned Hint = MRI->getSimpleHint(VirtReg);
89 return getPhys(VirtReg) == Hint;
92 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
93 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
101 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
102 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
103 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
105 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
106 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC)
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