| /external/lldb/test/python_api/lldbutil/iter/ |
| TestRegistersIterator.py | 56 for reg in REGs:
57 self.assertTrue(reg)
59 print "%s => %s" % (reg.GetName(), reg.GetValue())
65 for reg in REGs:
66 self.assertTrue(reg)
68 print "%s => %s" % (reg.GetName(), reg.GetValue())
74 for reg in REGs:
75 self.assertTrue(reg)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUAsmPrinter.cpp | 74 unsigned reg; local
79 reg = MO.getReg();
80 if (reg == AMDGPU::VCC) {
84 if (reg == AMDGPU::EXEC) {
87 if (AMDGPU::SReg_32RegClass.contains(reg)) {
90 } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
93 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
96 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
99 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
102 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
[all...] |
| SIRegisterInfo.cpp | 33 unsigned SIRegisterInfo::getBinaryCode(unsigned reg) const
35 switch (reg) {
38 default: return getHWRegNum(reg);
|
| /external/lldb/source/Target/ |
| RegisterContext.cpp | 70 for (uint32_t reg = start_idx; reg < num_registers; ++reg)
72 const RegisterInfo * reg_info = GetRegisterInfoAtIndex(reg);
85 RegisterContext::GetRegisterName (uint32_t reg)
87 const RegisterInfo * reg_info = GetRegisterInfoAtIndex(reg);
96 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); local
97 return ReadRegisterAsUnsigned (reg, fail_value);
103 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); local
104 bool success = WriteRegisterFromUnsigned (reg, pc)
119 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); local
126 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); local
133 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FP); local
140 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FP); local
147 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA); local
154 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS); local
219 const uint32_t reg = reg_set->registers[reg_idx]; local
[all...] |
| /external/lldb/source/Plugins/Process/POSIX/ |
| RegisterContext_x86_64.cpp | 302 #define GPR_i386_SIZE(reg) sizeof(((RegisterContext_i386::GPR*)NULL)->reg)
305 #define FPR_SIZE(reg) sizeof(((RegisterContext_x86_64::FXSAVE*)NULL)->reg)
317 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \
318 { #reg, alt, 0, 0, eEncodingUint, \
319 eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg }, NULL, NULL }
328 #define DEFINE_FPR(reg, kind1, kind2, kind3, kind4) \
329 { #reg, NULL, FPR_SIZE(reg), FPR_OFFSET(reg), eEncodingUint,
[all...] |
| /art/compiler/dex/quick/arm/ |
| int_arm.cc | 129 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh());
132 OpRegRegReg(kOpSub, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow());
146 rl_temp.reg.SetReg(t_reg.GetReg());
164 RegStorage low_reg = rl_src1.reg.GetLow();
165 RegStorage high_reg = rl_src1.reg.GetHigh();
251 OpRegRegImm(kOpSub, rl_result.reg, rl_src.reg, -true_val);
254 LoadConstant(rl_result.reg, false_val)
[all...] |
| /art/compiler/dex/ |
| reg_location.h | 52 RegStorage reg; // Encoded physical registers. member in struct:art::RegLocation
|
| /external/libunwind/src/aarch64/ |
| regname.c | 100 unw_regname (unw_regnum_t reg)
102 if (reg < (unw_regnum_t) ARRAY_SIZE (regname) && regname[reg] != NULL)
103 return regname[reg];
|
| /external/libunwind/src/ia64/ |
| Gregs.c | 31 linux_scratch_loc (struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr)
40 switch (reg)
46 *nat_bitnr = (reg - UNW_IA64_NAT);
52 addr += LINUX_SC_GR_OFF + 8 * (reg - UNW_IA64_GR);
56 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR);
78 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR);
90 if (unw_is_fpreg (reg))
91 return IA64_FPREG_LOC (c, reg);
93 return IA64_REG_LOC (c, reg);
101 if ((unsigned) (reg - UNW_IA64_NAT) < 128
[all...] |
| /external/libunwind/src/arm/ |
| Gresume.c | 119 int reg; local
123 for (reg = 0; reg <= UNW_REG_LAST; ++reg)
125 Debug (16, "copying %s %d\n", unw_regname (reg), reg);
126 if (unw_is_fpreg (reg))
128 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0)
129 as->acc.access_fpreg (as, reg, &fpval, 1, arg);
133 if (tdep_access_reg (c, reg, &val, 0) >= 0
[all...] |
| /external/libunwind/src/hppa/ |
| Gresume.c | 100 int reg; local
107 for (reg = 0; reg <= UNW_REG_LAST; ++reg)
109 Debug (16, "copying %s %d\n", unw_regname (reg), reg);
110 if (unw_is_fpreg (reg))
112 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0)
113 (*access_fpreg) (as, reg, &fpval, 1, arg);
117 if (tdep_access_reg (c, reg, &val, 0) >= 0
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocBase.cpp | 75 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
76 if (MRI->reg_nodbg_empty(Reg))
78 enqueue(&LIS->getInterval(Reg));
89 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
94 LIS->removeInterval(VirtReg->reg);
105 << MRI->getRegClass(VirtReg->reg)->getName()
116 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
129 VRM->assignVirt2Phys(VirtReg->reg,
130 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front())
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_eu.h | 196 struct brw_reg reg; local
204 reg.type = type;
205 reg.file = file;
206 reg.nr = nr;
207 reg.subnr = subnr * type_sz(type);
208 reg.negate = 0;
209 reg.abs = 0;
210 reg.vstride = vstride;
211 reg.width = width;
212 reg.hstride = hstride
[all...] |
| brw_vec4.cpp | 62 src_reg::src_reg(register_file file, int reg, const glsl_type *type)
67 this->reg = reg;
107 src_reg::src_reg(dst_reg reg)
111 this->file = reg.file;
112 this->reg = reg.reg;
113 this->reg_offset = reg.reg_offset;
114 this->type = reg.type
307 int reg = inst->src[i].reg; local
323 int reg = inst->dst.reg; local
[all...] |
| brw_wm_iz.c | 126 GLuint reg = 2; local
150 c->source_depth_reg = reg;
151 reg += 2;
158 c->aa_dest_stencil_reg = reg;
161 reg++;
165 c->dest_depth_reg = reg;
166 reg+=2;
169 c->nr_payload_regs = reg;
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_eu.h | 196 struct brw_reg reg; local
204 reg.type = type;
205 reg.file = file;
206 reg.nr = nr;
207 reg.subnr = subnr * type_sz(type);
208 reg.negate = 0;
209 reg.abs = 0;
210 reg.vstride = vstride;
211 reg.width = width;
212 reg.hstride = hstride
[all...] |
| brw_vec4.cpp | 62 src_reg::src_reg(register_file file, int reg, const glsl_type *type)
67 this->reg = reg;
107 src_reg::src_reg(dst_reg reg)
111 this->file = reg.file;
112 this->reg = reg.reg;
113 this->reg_offset = reg.reg_offset;
114 this->type = reg.type
307 int reg = inst->src[i].reg; local
323 int reg = inst->dst.reg; local
[all...] |
| brw_wm_iz.c | 126 GLuint reg = 2; local
150 c->source_depth_reg = reg;
151 reg += 2;
158 c->aa_dest_stencil_reg = reg;
161 reg++;
165 c->dest_depth_reg = reg;
166 reg+=2;
169 c->nr_payload_regs = reg;
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| radeon_cmdbuf.h | 20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
21 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
94 #define OUT_BATCH_REGVAL(reg, val) \
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
100 #define OUT_BATCH_REGSEQ(reg, count) \
101 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
|
| /external/elfutils/0.153/libdw/ |
| dwarf_frame_register.c | 81 const struct dwarf_frame_register *reg = &fs->regs[regno]; local
83 switch (reg->rule)
104 if (reg->value != 0)
106 .number = reg->value };
107 if (reg->rule == reg_val_offset)
115 .number = reg->value };
125 const uint8_t *p = fs->cache->data->d.d_buf + reg->value;
134 true, reg->rule == reg_val_expression,
|
| /external/linux-tools-perf/perf-3.12.0/arch/arm/lib/ |
| memcpy.S | 19 .macro ldr1w ptr reg abort
20 W(ldr) \reg, [\ptr], #4
31 .macro ldr1b ptr reg cond=al abort
32 ldr\cond\()b \reg, [\ptr], #1
35 .macro str1w ptr reg abort
36 W(str) \reg, [\ptr], #4
43 .macro str1b ptr reg cond=al abort
44 str\cond\()b \reg, [\ptr], #1
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_cmdbuf.h | 20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
21 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
94 #define OUT_BATCH_REGVAL(reg, val) \
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
100 #define OUT_BATCH_REGSEQ(reg, count) \
101 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
| r200_fragshader.c | 328 GLuint reg; local
333 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
334 if (shader->swizzlerq & (1 << (2 * reg)))
336 set_re_cntl_d3d( ctx, reg, 1);
338 else set_re_cntl_d3d( ctx, reg, 0);
364 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_fragshader.c | 328 GLuint reg; local
333 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
334 if (shader->swizzlerq & (1 << (2 * reg)))
336 set_re_cntl_d3d( ctx, reg, 1);
338 else set_re_cntl_d3d( ctx, reg, 0);
364 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++)
[all...] |
| /external/libunwind/tests/ |
| Gia64-test-stack.c | 59 int ret, reg, i, l; local
80 for (reg = 32; reg < 128; reg += 4)
85 ((ret = unw_get_reg (&c, UNW_IA64_GR + reg, &v0)) < 0
86 || (ret = unw_get_reg (&c, UNW_IA64_NAT + reg, &n0)) < 0
87 || (ret = unw_get_reg (&c, UNW_IA64_GR + reg + 1, &v1)) < 0
88 || (ret = unw_get_reg (&c, UNW_IA64_NAT + reg + 1, &n1)) < 0
89 || (ret = unw_get_reg (&c, UNW_IA64_GR + reg + 2, &v2)) < 0
90 || (ret = unw_get_reg (&c, UNW_IA64_NAT + reg + 2, &n2)) <
[all...] |
