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  /external/libunwind/src/ia64/
Ginit.c 49 tdep_uc_addr (ucontext_t *uc, int reg, uint8_t *nat_bitnr)
51 return inlined_uc_addr (uc, reg, nat_bitnr);
126 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write,
137 switch (reg)
140 if ((ret = __uc_get_grs (uc, (reg - UNW_IA64_GR), 1, &value, &nat)))
144 ret = __uc_set_grs (uc, (reg - UNW_IA64_GR), 1, val, nat);
150 if ((ret = __uc_get_grs (uc, (reg - UNW_IA64_GR), 1, &value, &nat)))
153 mask = 1 << (reg - UNW_IA64_GR);
161 ret = __uc_set_grs (uc, (reg - UNW_IA64_GR), 1, &value, nat);
168 if (reg == UNW_IA64_AR_BSP
    [all...]
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
brw_vec4_reg_allocate.cpp 37 assign(unsigned int *reg_hw_locations, reg *reg)
39 if (reg->file == GRF) {
40 reg->reg = reg_hw_locations[reg->reg];
63 virtual_grf_used[inst->dst.reg] = true;
67 virtual_grf_used[inst->src[i].reg] = true;
121 int reg = 0 local
210 int reg = choose_spill_reg(g); local
226 int reg = ra_get_node_reg(g, i); local
    [all...]
brw_clip_util.c 76 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1));
77 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1));
78 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1));
79 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1));
80 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1));
81 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1));
227 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
237 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
239 c->reg.R0,
263 c->reg.R0
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_vec4_reg_allocate.cpp 37 assign(unsigned int *reg_hw_locations, reg *reg)
39 if (reg->file == GRF) {
40 reg->reg = reg_hw_locations[reg->reg];
63 virtual_grf_used[inst->dst.reg] = true;
67 virtual_grf_used[inst->src[i].reg] = true;
121 int reg = 0 local
210 int reg = choose_spill_reg(g); local
226 int reg = ra_get_node_reg(g, i); local
    [all...]
brw_clip_util.c 76 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1));
77 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1));
78 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1));
79 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1));
80 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1));
81 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1));
227 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
237 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
239 c->reg.R0,
263 c->reg.R0
    [all...]
  /art/compiler/dex/quick/mips/
int_mips.cc 51 NewLIR3(kMipsSlt, t0.GetReg(), rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg());
52 NewLIR3(kMipsSlt, t1.GetReg(), rl_src2.reg.GetHighReg(), rl_src1.reg.GetHighReg());
53 NewLIR3(kMipsSubu, rl_result.reg.GetReg(), t1.GetReg(), t0.GetReg());
54 LIR* branch = OpCmpImmBranch(kCondNe, rl_result.reg, 0, NULL);
55 NewLIR3(kMipsSltu, t0.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg());
56 NewLIR3(kMipsSltu, t1.GetReg(), rl_src2.reg.GetLowReg(), rl_src1.reg.GetLowReg())
    [all...]
  /art/runtime/arch/arm/
context_arm.cc 72 bool ArmContext::SetGPR(uint32_t reg, uintptr_t value) {
73 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
74 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
75 if (gprs_[reg] != nullptr) {
76 *gprs_[reg] = value;
83 bool ArmContext::SetFPR(uint32_t reg, uintptr_t value) {
84 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfSRegisters));
85 DCHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
86 if (fprs_[reg] != nullptr) {
87 *fprs_[reg] = value
    [all...]
  /art/runtime/arch/mips/
context_mips.cc 71 bool MipsContext::SetGPR(uint32_t reg, uintptr_t value) {
72 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
73 CHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
74 if (gprs_[reg] != nullptr) {
75 *gprs_[reg] = value;
82 bool MipsContext::SetFPR(uint32_t reg, uintptr_t value) {
83 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFRegisters));
84 CHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
85 if (fprs_[reg] != nullptr) {
86 *fprs_[reg] = value
    [all...]
  /external/ltrace/sysdeps/linux-gnu/arm/
regs.c 43 arm_get_register(struct process *proc, enum arm_register reg, uint32_t *lp)
46 long l = ptrace(PTRACE_PEEKUSER, proc->pid, (void *)(reg * 4L), 0);
54 arm_set_register(struct process *proc, enum arm_register reg, uint32_t lp)
57 (void *)(reg * 4L), (void *)lp);
61 arm_get_register_offpc(struct process *proc, enum arm_register reg,
64 if (arm_get_register(proc, reg, lp) < 0)
66 if (reg == ARM_REG_PC)
126 uint32_t reg; local
127 if (arm_get_register(proc, r, &reg) < 0)
131 return (arch_addr_t)(uintptr_t)reg;
    [all...]
  /art/compiler/dex/quick/x86/
int_x86.cc 41 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
42 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0
44 NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg());
45 NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg());
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg,
108 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode
109 NewLIR2(reg.Is64Bit() ? kX86Test64RR: kX86Test32RR, reg.GetReg(), reg.GetReg())
    [all...]
  /external/smack/src/org/jivesoftware/smack/
AccountManager.java 226 Registration reg = new Registration(); local
227 reg.setType(IQ.Type.SET);
228 reg.setTo(connection.getServiceName());
231 reg.setAttributes(attributes);
232 PacketFilter filter = new AndFilter(new PacketIDFilter(reg.getPacketID()),
235 connection.sendPacket(reg);
256 Registration reg = new Registration(); local
257 reg.setType(IQ.Type.SET);
258 reg.setTo(connection.getServiceName());
262 reg.setAttributes(map)
290 Registration reg = new Registration(); local
318 Registration reg = new Registration(); local
    [all...]
  /frameworks/native/opengl/tools/glgen2/
glgen.py 30 import reg namespace
104 class TrampolineGen(reg.OutputGenerator):
106 reg.OutputGenerator.__init__(self, sys.stderr, sys.stderr, None)
109 reg.OutputGenerator.genCmd(self, cmd, name)
128 class ApiGenerator(reg.OutputGenerator):
130 reg.OutputGenerator.__init__(self, sys.stderr, sys.stderr, None)
135 reg.OutputGenerator.genCmd(self, cmd, name)
141 reg.OutputGenerator.genEnum(self, enuminfo, name)
215 class SpecGenerator(reg.OutputGenerator):
217 reg.OutputGenerator.__init__(self, sys.stderr, sys.stderr, None
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/svga/svgadump/
svga_shader_dump.c 131 const struct sh_reg reg,
134 if (reg.relative) {
138 _debug_printf("%s[aL+%u]", name, reg.number);
140 _debug_printf("%s[a%u.x+%u]", name, indreg->number, reg.number);
143 _debug_printf("%s%u", name, reg.number);
147 static void dump_reg( struct sh_reg reg, struct sh_srcreg *indreg, const struct dump_info *di )
149 assert( reg.is_reg == 1 );
151 switch (sh_reg_type( reg )) {
153 format_reg("r", reg, NULL);
157 format_reg("v", reg, indreg)
361 struct sh_reg reg; member in union:__anon17753
    [all...]
  /external/mesa3d/src/gallium/drivers/svga/svgadump/
svga_shader_dump.c 131 const struct sh_reg reg,
134 if (reg.relative) {
138 _debug_printf("%s[aL+%u]", name, reg.number);
140 _debug_printf("%s[a%u.x+%u]", name, indreg->number, reg.number);
143 _debug_printf("%s%u", name, reg.number);
147 static void dump_reg( struct sh_reg reg, struct sh_srcreg *indreg, const struct dump_info *di )
149 assert( reg.is_reg == 1 );
151 switch (sh_reg_type( reg )) {
153 format_reg("r", reg, NULL);
157 format_reg("v", reg, indreg)
361 struct sh_reg reg; member in union:__anon31312
    [all...]
  /external/chromium_org/third_party/mesa/src/src/mapi/glapi/gen/
gl_x86-64_asm.py 33 for [reg, offset] in registers:
34 if reg[1:4] == "xmm":
58 for [reg, stack_offset] in registers:
59 save_reg( reg, stack_offset, adjust_stack )
70 [reg, stack_offset] = temp.pop()
71 restore_reg(reg, stack_offset, adjust_stack)
78 def save_reg(reg, offset, use_move):
81 print '\tmovq\t%s, (%%rsp)' % (reg)
83 print '\tmovq\t%s, %u(%%rsp)' % (reg, offset)
85 print '\tpushq\t%s' % (reg)
    [all...]
  /external/libunwind/src/x86/
Ginit.c 50 tdep_uc_addr (ucontext_t *uc, int reg)
52 return x86_r_uc_addr (uc, reg);
190 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write,
196 if (unw_is_fpreg (reg))
199 if (!(addr = x86_r_uc_addr (uc, reg)))
205 Debug (12, "%s <- %x\n", unw_regname (reg), *val);
210 Debug (12, "%s -> %x\n", unw_regname (reg), *val);
215 Debug (1, "bad register number %u\n", reg);
220 access_fpreg (unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val,
226 if (!unw_is_fpreg (reg))
    [all...]
  /external/mesa3d/src/mapi/glapi/gen/
gl_x86-64_asm.py 33 for [reg, offset] in registers:
34 if reg[1:4] == "xmm":
58 for [reg, stack_offset] in registers:
59 save_reg( reg, stack_offset, adjust_stack )
70 [reg, stack_offset] = temp.pop()
71 restore_reg(reg, stack_offset, adjust_stack)
78 def save_reg(reg, offset, use_move):
81 print '\tmovq\t%s, (%%rsp)' % (reg)
83 print '\tmovq\t%s, %u(%%rsp)' % (reg, offset)
85 print '\tpushq\t%s' % (reg)
    [all...]
  /external/libpcap/msdos/
pktdrvr.c 150 LOCAL SWI_REGS reg; variable
156 static __dpmi_regs reg; variable
171 LOCAL struct DPMI_regs reg; variable in typeref:struct:DPMI_regs
185 } reg; variable in typeref:struct:__anon28391
312 _dx_real_int ((UINT)pktInfo.intr, &reg);
313 okay = ((reg.flags & 1) == 0); /* OK if carry clear */
316 __dpmi_int ((int)pktInfo.intr, &reg);
317 okay = ((reg.x.flags & 1) == 0);
328 s.es = FP_SEG (&reg);
329 r.x.edi = FP_OFF (&reg);
    [all...]
  /system/core/libpixelflinger/codeflinger/
texturing.cpp 88 parts.argb[i].reg = c;
91 parts.argb_dx[i].reg = (parts.reload & 2) ? t1 : obtainReg();
92 const int dvdx = parts.argb_dx[i].reg;
94 MLA(AL, 0, c, x.reg, dvdx, c);
102 MOV(AL, 0, end, reg_imm(parts.count.reg, LSR, 16));
136 CONTEXT_LOAD(parts.iterated.reg, packed8888);
160 CONTEXT_LOAD(parts.iterated.reg, packed);
162 AND(AL, 0, parts.iterated.reg,
163 parts.iterated.reg, imm(0xFF));
165 MOV(AL, 0, parts.iterated.reg,
    [all...]
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
r200_sanity.c 602 struct reg { struct
614 static struct reg regs[Elements(reg_names)+1];
615 static struct reg scalars[512+1];
616 static struct reg vectors[512*4+1];
650 static int find_or_add_value( struct reg *reg, int val )
654 for ( j = 0 ; j < reg->nvalues ; j++)
655 if ( val == reg->values[j].i )
658 if (j == reg->nalloc) {
659 reg->nalloc += 5
828 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); local
856 struct reg *reg = lookup_reg( scalars, start ); local
888 struct reg *reg = lookup_reg( scalars, start ); local
924 struct reg *reg = lookup_reg( vectors, start*4+j ); local
    [all...]
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
radeon_sanity.c 324 struct reg { struct
336 static struct reg regs[Elements(reg_names)+1];
337 static struct reg scalars[512+1];
338 static struct reg vectors[512*4+1];
372 static int find_or_add_value( struct reg *reg, int val )
376 for ( j = 0 ; j < reg->nvalues ; j++)
377 if ( val == reg->values[j].i )
380 if (j == reg->nalloc) {
381 reg->nalloc += 5
550 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); local
578 struct reg *reg = lookup_reg( scalars, start ); local
610 struct reg *reg = lookup_reg( scalars, start ); local
646 struct reg *reg = lookup_reg( vectors, start*4+j ); local
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_sanity.c 602 struct reg { struct
614 static struct reg regs[Elements(reg_names)+1];
615 static struct reg scalars[512+1];
616 static struct reg vectors[512*4+1];
650 static int find_or_add_value( struct reg *reg, int val )
654 for ( j = 0 ; j < reg->nvalues ; j++)
655 if ( val == reg->values[j].i )
658 if (j == reg->nalloc) {
659 reg->nalloc += 5
828 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); local
856 struct reg *reg = lookup_reg( scalars, start ); local
888 struct reg *reg = lookup_reg( scalars, start ); local
924 struct reg *reg = lookup_reg( vectors, start*4+j ); local
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_sanity.c 324 struct reg { struct
336 static struct reg regs[Elements(reg_names)+1];
337 static struct reg scalars[512+1];
338 static struct reg vectors[512*4+1];
372 static int find_or_add_value( struct reg *reg, int val )
376 for ( j = 0 ; j < reg->nvalues ; j++)
377 if ( val == reg->values[j].i )
380 if (j == reg->nalloc) {
381 reg->nalloc += 5
550 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); local
578 struct reg *reg = lookup_reg( scalars, start ); local
610 struct reg *reg = lookup_reg( scalars, start ); local
646 struct reg *reg = lookup_reg( vectors, start*4+j ); local
    [all...]
  /external/valgrind/main/memcheck/tests/amd64/
bt_everything.c 171 /* ------------ REG, Q ------------ */
246 /* ------------ REG, L ------------ */
321 /* ------------ REG, W ------------ */
410 ULong reg; local
454 /*------------------------ REG-L -----------------------*/
457 reg = 0;
464 case 0: c = btsl_reg(reg, bitoff, &reg); break;
465 case 1: c = btrl_reg(reg, bitoff, &reg); break
    [all...]
  /art/compiler/dex/quick/arm/
fp_arm.cc 65 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
112 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
142 RegisterInfo* info = GetRegInfo(rl_src.reg);
152 NewLIR2(kThumb2VcvtF64U32, rl_result.reg.GetReg(), src_low.GetReg());
154 NewLIR3(kThumb2VmlaF64, rl_result.reg.GetReg(), tmp1.GetReg(), tmp2.GetReg());
165 RegisterInfo* info = GetRegInfo(rl_src.reg);
    [all...]

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1 2 3 4 5 6 78 91011>>